epic.c

Infineon公司有一款实现SHDSL协议（ADSL协议的变种）的芯片

/*******************************************************************************
       Copyright (c) 2000, Infineon Technologies.  All rights reserved.
  
                               No Warranty                                                 
   Because the program is licensed free of charge, there is no warranty for 
   the program, to the extent permitted by applicable law.  Except when     
   otherwise stated in writing the copyright holders and/or other parties   
   provide the program "as is" without warranty of any kind, either         
   expressed or implied, including, but not limited to, the implied         
   warranties of merchantability and fitness for a particular purpose. The  
   entire risk as to the quality and performance of the program is with     
   you.  should the program prove defective, you assume the cost of all     
   necessary servicing, repair or correction.                               
                                                                            
   In no event unless required by applicable law or agreed to in writing    
   will any copyright holder, or any other party who may modify and/or      
   redistribute the program as permitted above, be liable to you for        
   damages, including any general, special, incidental or consequential     
   damages arising out of the use or inability to use the program           
   (including but not limited to loss of data or data being rendered        
   inaccurate or losses sustained by you or third parties or a failure of   
   the program to operate with any other programs), even if such holder or  
   other party has been advised of the possibility of such damages. 
 *******************************************************************************       
   
   Module:        EPIC
   Product ID:    22622.1.0.1
   Description:   Contains EPIC access. 

 ******************************************************************************/

//  Group= EPIC 

/* ============================= */
/* Includes                      */
/* ============================= */

#include <stdio.h>
#include <absacc.h>

#include "sysdef.h"            
#include "dds.h"          
#include "sysvar.h"
#include "sysfunc.h"

#include "modid.h"

/* ============================= */
/* Local Macros & Definitions    */
/* ============================= */

#define PCM         0x00
#define CFI         0x01
#define CFI_Port1   0x11

/* ============================= */
/* Local variable definition     */
/* ============================= */

                                      /* @globalv WORD8 | Epic_delay_mode |
                                         Set to 1 if PCM 4MHz mode 
                                         initialized and const. delay
                                         switching in upstream direction
                                         is necessary                      */
static WORD8 Epic_extra_switching;

                                      /*  @globalv WORD8 | Epic_Pcm_Mode | 
                                          Stores the PCM mode of EPIC      */
static WORD8 Epic_Pcm_Mode;

                                      /*  @globalv WORD8 | Epic_Cfi_Mode | 
                                          Stores the CFI mode of EPIC      */
static WORD8 Epic_Cfi_Mode;

/* ============================= */
/* Local function declaration    */
/* ============================= */

static void  Epic_Set_Single_Connection (WORD8 src_port, WORD8 src_slot, WORD8 dst_port, WORD8 dst_slot);
static void  Epic_Reset_All_Connections (void);
static WORD8 Epic_Encode_Time_Slot (WORD8 type, WORD8 port, WORD8 slot);

/* ============================= */
/* Global function definition    */
/* ============================= */

/*******************************************************************************
Description: 
   Inititialization function of the epic module.
Arguments:
   NONE.
Return:
   NONE.
Remarks:
   This function initializes the EPIC according to the 
   board configuration settings.
 ******************************************************************************/
void Epic_Init (void)
{
                                      /* PCM mode0,                    
                                         PCM single clock,             
                                         eval. PFS with fall. PDC edge,
                                         no altern. inp selection,     
                                         no altern. inp comparison.        */
   if (G_Eeprom [CONFIG_P_CLK] == P_CLK_2MHZ)
   {
      Out ( EPIC_PMOD , 0x00 );
      Epic_Pcm_Mode = 0;
                                      /* Set PCM offset downstream.        */
      Out(EPIC_POFD , 0xF1);               
                                      /* Set PCM offset upstream.          */
      Out(EPIC_POFU , 0x19);               
   }

                                      /* PCM mode1,                    
                                         set altern. inp selection.        */
   if (G_Eeprom [CONFIG_P_CLK] == P_CLK_4MHZ)
   {
      Out ( EPIC_PMOD , 0x44 );
      Epic_Pcm_Mode = 1;
                                      /* Set PCM offset downstream.        */  
      Out(EPIC_POFD , 0xF0);               
                                      /* Set PCM offset upstream.          */
      Out(EPIC_POFU , 0x18);               
   }

                                      /* Sample PCM data with          
                                         falling edge of PDC, transmit 
                                         PCM data with rising          
                                         edge of PDC.                      */
   Out(EPIC_PCSR , 0x67);
   
   
                                      /* Set PCM frame bit number.     
                                         256 bits per PCM frame:       
                                         -> 2Mbps(mode0), 4Mbps(mode1)     */
   Out(EPIC_PBNR , 0xFF); 



                                      /* Sample PCM data with          
                                         falling edge of PDC, transmit 
                                         PCM data with rising          
                                         edge of PDC.                      */
   Out(EPIC_PCSR , 0x67);

                                      /* DCL & FSC selected as clock,  
                                         FSC eval. with fall. PDC edge,
                                         prescale divisor 1,           
                                         no altern. input selection.   
                                         CFI mode1.                        */
   Out(EPIC_CMD1 , 0xA4);

   if (G_Eeprom [CONFIG_P_CLK] == P_CLK_2MHZ)
   {
                                      /* CFI transmission on           
                                         rising CRCL edge, CFI receive 
                                         on falling CRCL edge,         
                                         256 bits per CFI frame.       
                                         -> 2Mbps(mode1)                   */
      Out(EPIC_CMD2 , 0x00);
      Epic_Cfi_Mode = 1;
   }

   if (G_Eeprom [CONFIG_P_CLK] == P_CLK_4MHZ)
   {
                                      /* 512 bits per CFI frame.       
                                         -> 4Mbps(mode1)                   */
      Out(EPIC_CMD2 , 0x01);
      Epic_Cfi_Mode = 1;
   }
   
                                      /* No CFI downstream frame       
                                         bit shifts.                       */                   
   Out(EPIC_CBSR , 0x30);               
      
                                      /* 256 or 512 bits per CFI frame 
                                         depending on CMD2 register.       */
   Out(EPIC_CBNR , 0xFF);

                                      /* Mark time slot nr. 0.             */
   Out(EPIC_CTAR , 0x02);


                                      /* Disable subchannel control.       */
   Out(EPIC_CSCR , 0x00);

                                      /* Memory access registers.      
                                         CM data + code reset.             */
   Out(EPIC_MADR , 0xFF);
   Out(EPIC_MACR , 0x70);
   WHILE_NOT_ABORT ( In(EPIC_STAR) > 0x7F);
   if (G_Abort == TRUE) printf(": EPIC_STAR0\n");    
   
                                      /* CM test mode, PCM output high 
                                         impedance, test loop disabled,
                                         CFI tristate drivers, handsh. 
                                         facility disabled, CFI output 
                                         to high impedance, access reg 
                                         during operation.                 */
   Out(EPIC_OMDR , 0x40); 

                                      /* Memory access registers:      
                                         DM data reset.                    */
   Out(EPIC_MADR , 0x00);
   Out(EPIC_MACR , 0x08);
   WHILE_NOT_ABORT ( In(EPIC_STAR) > 0x7F);
   if (G_Abort == TRUE) printf(": EPIC_STAR1\n");    

                                      /* CM normal operation mode.         */
   Out ( EPIC_OMDR , ( In(EPIC_OMDR) | 0xC0 ) );
   WHILE_NOT_ABORT ( In(EPIC_STAR) != 0x25);
   if (G_Abort == TRUE) printf(": EPIC_STAR2\n");    

                                      /* If EPIC is in normal oper.    
                                         mode: EPIC has clocks.            */
   if (G_Abort == FALSE)
   {
                                      /* Memory access registers.      
                                         DM code reset.                    */
      Out (EPIC_MADR , 0x00);
      Out (EPIC_MACR , 0x68);
      WHILE_NOT_ABORT ( In (EPIC_STAR) > 0x7F);
      if (G_Abort == TRUE) printf(": EPIC_STAR3\n");    

                                      /* CM normal operation mode,     
                                         PCM output pins open, CFI     
                                         output pins are active.           */
      Out (EPIC_OMDR , ( In (EPIC_OMDR) | 0xE2 ) );

                                      /* Disable timer int. generation,
                                         reset signalling FIFO,        
                                         reset MFFIFO.                     */
      Out (EPIC_CMDR , 0x11);
      WHILE_NOT_ABORT ( In(EPIC_STAR) > 0x7F);
      if (G_Abort == TRUE) printf(": EPIC_STAR4\n");    

                                      /* Demask all interrupts.            */
      Out (EPIC_MASK , 0x00);

                                      /* Reset all timeslot connection     */
      Epic_Reset_All_Connections ();
   }