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📄 falc.c

📁 Infineon公司有一款实现SHDSL协议(ADSL协议的变种)的芯片
💻 C
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                                          enable all IMR2 interrupts,   
                                          enable ES and SEC interrupts, 
                                          enable all IMR4 interrupts.         */
        Out(FALC_IMR2, 0x00);
        Out(FALC_IMR3, In(FALC_IMR3) & ~0xC0);
        Out(FALC_IMR4, 0x00);
                                       /* Command register:              
                                          receiver, transmitter and     
                                          signalling transmitter reset.       */
        Out(FALC_CMDR,  0x51);
      break;


    case INTF_T1_PCM_PLE:
        
                                       /* SIC1: Transmit Buffer Size: 
                                          2 frames                            */
        Out(FALC_SIC1, 0x02);
                                       /* SIC2: Select System Clock
                                          1.544 MHz                           */
        Out(FALC_SIC2, 0x10);
                                       /* PC6: Select System Clock            */
        Out(FALC_PC6,  0x01);       
                                       /* Frame mode register 1:         
                                          PCM 24 mode,
                                          CRC6 enabled, 
                                          System interface mode         
                                          is 1.544Mbit/s.                         */        
        Out(FALC_FMR1, 0x98);
        Out(FALC_SIC3, 0x04);
        
                                      /* Frame mode register 0:         
                                         transmit and receive code     
                                         is B8ZS Code.                       */
        Out(FALC_FMR0, 0xF0);                                       
                                      /* Frame mode register 2:         
                                         sync on framing candidate,
                                         no CRC6 errors.                     */
        Out(FALC_FMR2, 0x60);
                                      /* Transmit service word pulse:   
                                         enable auto resync,
                                         LFA if 2 out of 5.                  
                                         ESF frame mode                      */
        Out(FALC_XSW , 0x8E);
                                      /* all bits set to normal operation,    
                                         /SYPX define the frame              */
        Out(FALC_XSP , 0x00);

                                       /* Transmit control 0+1:          
                                          timeslot 0 is starting with   
                                          SYPQ in transmit direction.   
                                          !!! Adapt to board !!!              */
        
                                      /* Transmit counter offset       
                                          is 6 (PCM clock 2 MHz).             */  
        Out(FALC_XC0 , 0x00);
        Out(FALC_XC1 , 0x0A);
                                  
                                       /* Receive control 0+1:           
                                          timeslot 0 is starting with   
                                          SYPQ in receive direction.    
                                          !!! Adapt to board !!!              */
    
                                       /* Transmit counter offset       
                                          is 3                                */  
        Out(FALC_RC0 , 0x84);
        Out(FALC_RC1 , 0x0B);
    


                                      /* Set characteristic of data path A.  */
        
                                      /* /SYPR output, /SYPX input           */
        Out(FALC_PC1,  0x10);
                                       /* /SCLKR output                       */
        Out(FALC_PC5,  0x33);

                                       /* internal clock system sourced by: 
                                          transmit: /SYPX /SCLKX
                                          receive: DCO-R                      */
        Out(FALC_CMR2 ,0x0C);
                                       /* RCLK recovered from DCO-R           */
        Out(FALC_CMR1 ,0x20);
        
        
        
                                       /* Interrupt port configuration:  
                                          push/pull output, active low,
                                          for LOS recovery, SYNC freq = 8kHz. */
        Out(FALC_IPC , 0x05);
                                      /* Line interface mode 0:         
                                         master mode: slave mode,
                                         receiver sensitivity -36 dB.           */
        Out(FALC_LIM0, 0x08);

        
                                      /* Line interface mode 1:         
                                         receive input threshold 0.5V.        */
        Out(FALC_LIM1, 0x30);
                                      
                                      /* Line interface mode 2:         
                                         recovery with additional no more 
                                         than 15 zeros (acc. Bellcore).      */
        Out(FALC_LIM2, 0x01);




                                       /* GPC1: FSC Output active Low         */
        Out(FALC_GPC1, 0x60);
        Out(FALC_CMDR2,0x00);
        


                                      /* Transmit pulse mask 0-2.            */
        Out(FALC_XPM0, 0x7D);
        Out(FALC_XPM1, 0xAB);
        Out(FALC_XPM2, 0x01);

        

                                       /* Pulse count detection:         
                                          LOS detection after 176       
                                          consecutive 0s.                     */
        Out(FALC_PCD , 0x0A);

                                      /* Pulse count recovery:          
                                         LOS recovery after 22         
                                         consecutive 1s.                     */
        Out(FALC_PCR , 0x15);
        
                                      /* Interrupt mask register 2-4:   
                                         enable all IMR2 interrupts,   
                                         enable ES and SEC interrupts, 
                                         enable all IMR4 interrupts.         */
        Out(FALC_IMR2, 0x00);
        Out(FALC_IMR3, In(FALC_IMR3) & ~0xC0);
        Out(FALC_IMR4, 0x00);
                                      /* Command register:              
                                         receiver, transmitter and     
                                         signalling transmitter reset.       */
        Out(FALC_CMDR, 0x51);
      break;


      case INTF_T1:
                                       /* SIC1: Transmit Buffer Size: 
                                          2 frames                            */
        Out(FALC_SIC1, 0x02);
                                       /* SIC2: Select System Clock
                                          1.544 MHz                           */
        Out(FALC_SIC2, 0x10);
                                       /* PC6: Select System Clock            */
        Out(FALC_PC6,  0x01);       
                                       /* Frame mode register 1:         
                                          PCM 24 mode,
                                          CRC6 enabled, 
                                          System interface mode         
                                          is 1.544Mbit/s.                         */        
        Out(FALC_FMR1, 0x98);
        Out(FALC_SIC3, 0x04);
        
                                      /* Frame mode register 0:         
                                         transmit and receive code     
                                         is B8ZS Code.                       */
        Out(FALC_FMR0, 0xF0);                                       
                                      /* Frame mode register 2:         
                                         sync on framing candidate,
                                         no CRC6 errors.                     */
        Out(FALC_FMR2, 0x60);
                                      /* Transmit service word pulse:   
                                         enable auto resync,
                                         LFA if 2 out of 5.                  
                                         ESF frame mode                      */
        Out(FALC_XSW , 0x8E);
                                      /* all bits set to normal operation,    
                                         /SYPX define the frame              */
        Out(FALC_XSP , 0x00);





                                       /* Transmit control 0+1:          
                                          timeslot 0 is starting with   
                                          SYPQ in transmit direction.   
                                          !!! Adapt to board !!!              */
        if (G_Eeprom[CONFIG_MODE] == MODE_COT_EXT)
        {
                                       /* Transmit counter offset       
                                          is 6 (PCM clock 2 MHz).             */  
                Out(FALC_XC0 ,  0x00);
                Out(FALC_XC1 ,  0x0B);
        }
        else
        {
                                      /* Transmit counter offset       
                                          is 6 (PCM clock 2 MHz).             */  
                Out(FALC_XC0 ,  0x00);
                Out(FALC_XC1 ,  0x0A);
        }                          
                                       /* Receive control 0+1:           
                                          timeslot 0 is starting with   
                                          SYPQ in receive direction.    
                                          !!! Adapt to board !!!              */
        if (G_Eeprom[CONFIG_MODE] == MODE_COT_EXT)
        {                              /* Transmit counter offset       
                                          is 3                                */  
                Out(FALC_RC0 ,  0x84);
                Out(FALC_RC1 ,  0x0B);
        }
        else
        {
                                       /* Transmit counter offset       
                                          is 3                                */  
                Out(FALC_RC0 ,  0x84);
                Out(FALC_RC1 ,  0x0C);
        }


                                       /* Set characteristic of data path A.  */
        if (G_Eeprom[CONFIG_MODE] == MODE_COT_EXT)
        {
                                       /* RFM output, /SYPX input             */
            Out(FALC_PC1,  0x10);
                                       /* /SCLKR output                       */
            Out(FALC_PC5,  0x33);
                                       /* internal clock system sourced by 
                                          DCO-R                               */
            Out(FALC_CMR2, 0x0C);
        }
        else
        {
                                       /* /SYPR input, /SYPX input            */
            Out(FALC_PC1,  0x00);
                                       /* /SCLKR input                        */
            Out(FALC_PC5,  0x31);

                                       /* internal clock system sourced by 
                                          /SYPR                               */
            Out(FALC_CMR2, 0x00);
                                       /* RCLK recovered from DCO-R           */
            Out(FALC_CMR1, 0x20);
        }
        
        if (G_Eeprom[CONFIG_MODE] == MODE_COT_EXT)
        {   
                                       /* Interrupt port configuration:  
                                          push/pull output, active low,
                                          for LOS recovery, SYNC freq = 2MHz. */
            Out(FALC_IPC ,  0x01);          
                                       /* Line interface mode 0:         
                                          master mode/master mode,
                                          receiver sensitivity -36 dB.           */            
            Out(FALC_LIM0,  0x09);
        }
        else
        {
                                       /* Interrupt port configuration:  
                                          push/pull output, active low,
                                          for LOS recovery, SYNC freq = 8kHz. */
            Out(FALC_IPC ,  0x05);
                                       /* Line interface mode 0:         
                                          master mode/master mode,
                                          receiver sensitivity -36 dB.           */
            Out(FALC_LIM0,  0x09);

        }
                                       /* Line interface mode 1:         
                                          receive input threshold 0.5V.        */
        Out(FALC_LIM1,  0x30);
                                       
                                       /* Line interface mode 2:         
                                          recovery with additional no more 
                                          than 15 zeros (acc. Bellcore).      */
        Out(FALC_LIM2,  0x01);




                                       /* GPC1: FSC Output active Low         */
        Out(FALC_GPC1,  0x60);
        Out(FALC_CMDR2, 0x00);
        


                                       /* Transmit pulse mask 0-2.            */
        Out(FALC_XPM0,  0x7D);
        Out(FALC_XPM1,  0xAB);
        Out(FALC_XPM2,  0x01);

        

                                       /* Pulse count detection:         
                                          LOS detection after 176       
                                          consecutive 0s.                     */
        Out(FALC_PCD ,  0x0A);

                                       /* Pulse count recovery:          
                                          LOS recovery after 22         
                                          consecutive 1s.                     */
        Out(FALC_PCR ,  0x15);
        
                                       /* Interrupt mask register 2-4:   
                                          enable all IMR2 interrupts,   
                                          enable ES and SEC interrupts, 
                                          enable all IMR4 interrupts.         */
        Out(FALC_IMR2,  0x00);
        Out(FALC_IMR3,  In(FALC_IMR3) & ~0xC0);
        Out(FALC_IMR4,  0x00);
                                       /* Command register:              
                                          receiver, transmitter and     
                                          signalling transmitter reset.       */
        Out(FALC_CMDR,  0x51);
      break;

   default:
      printf("\nError FALC init: this mode is under construction :))");
      break;
    }
}

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