📄 falc.c
字号:
sync on framing candidate,
no CRC6 errors. */
Out(FALC_FMR2, 0x60);
/* Transmit service word pulse:
enable auto resync,
LFA if 2 out of 5.
ESF frame mode */
Out(FALC_XSW , 0x8E);
/* all bits set to normal operation,
/SYPX define the frame */
Out(FALC_XSP , 0x00);
/* Transmit control 0+1:
timeslot 0 is starting with
SYPQ in transmit direction.
!!! Adapt to board !!! */
if (G_Eeprom[CONFIG_MODE] == MODE_COT_EXT)
{
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_2MHZ)
{
/* Transmit counter offset
is 6 (PCM clock 2 MHz). */
Out(FALC_XC0 , 0x00);
Out(FALC_XC1 , 0x04);
}
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_4MHZ)
{
/* Transmit counter offset
is 3 (PCM clock 4 MHz). */
Out(FALC_XC0 , 0x00);
Out(FALC_XC1 , 0x04);
}
}
else
{
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_2MHZ)
{
/* Transmit counter offset
is 6 (PCM clock 2 MHz). */
Out(FALC_XC0 , 0x00);
Out(FALC_XC1 , 0x03);
}
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_4MHZ)
{
/* Transmit counter offset
is 3 (PCM clock 4 MHz). */
Out(FALC_XC0 , 0x00);
Out(FALC_XC1 , 0x03);
}
}
/* Receive control 0+1:
timeslot 0 is starting with
SYPQ in receive direction.
!!! Adapt to board !!! */
if (G_Eeprom[CONFIG_MODE] == MODE_COT_EXT)
{
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_2MHZ)
{
/* Transmit counter offset
is 3 (PCM clock 2 MHz). */
Out(FALC_RC0 , 0x84);
Out(FALC_RC1 , 0x04);
}
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_4MHZ)
{
/* Transmit counter offset
is 1 (PCM clock 4 MHz). */
Out(FALC_RC0 , 0x84);
Out(FALC_RC1 , 0x05);
}
}
else
{
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_2MHZ)
{
/* Transmit counter offset
is 3 (PCM clock 2 MHz). */
Out(FALC_RC0 , 0x84);
Out(FALC_RC1 , 0x04);
}
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_4MHZ)
{
/* Transmit counter offset
is 1 (PCM clock 4 MHz). */
Out(FALC_RC0 , 0x84);
Out(FALC_RC1 , 0x04);
}
}
/* Set characteristic of data path A. */
if (G_Eeprom[CONFIG_MODE] == MODE_COT_EXT)
{
/* RFM output, /SYPX input */
Out(FALC_PC1, 0x10);
/* /SCLKR output */
Out(FALC_PC5, 0x33);
/* internal clock system sourced by
DCO-R */
Out(FALC_CMR2, 0x0F);
}
else
{
/* /SYPR input, /SYPX input */
Out(FALC_PC1, 0x00);
/* /SCLKR output */
Out(FALC_PC5, 0x31);
/* internal clock system sourced by
/SYPR */
Out(FALC_CMR2, 0x00);
/* RCLK recovered from DCO-R */
Out(FALC_CMR1, 0x20);
}
if (G_Eeprom[CONFIG_MODE] == MODE_COT_EXT)
{
/* Interrupt port configuration:
push/pull output, active low,
for LOS recovery, SYNC freq = 2MHz. */
Out(FALC_IPC , 0x01);
/* Line interface mode 0:
master mode/master mode,
receiver sesivity -36 dB. */
Out(FALC_LIM0, 0x08);
}
else
{
/* Interrupt port configuration:
push/pull output, active low,
for LOS recovery, SYNC freq = 8kHz. */
Out(FALC_IPC , 0x05);
/* Line interface mode 0:
master mode/master mode,
receiver sensitivity -36 dB. */
Out(FALC_LIM0, 0x09);
}
/* Line interface mode 1:
receive input threshold 0.5V. */
Out(FALC_LIM1, 0x30);
/* Line interface mode 1:
enable to synchronize the internal
generated system clocks to pin
SYNC */
/* if (G_Eeprom[CONFIG_MODE] != MODE_COT_EXT)
Out(FALC_LIM1, In(FALC_LIM1) | 0x08); */
/* Line interface mode 2:
recovery with additional no more
than 15 zeros (acc. Bellcore). */
Out(FALC_LIM2, 0x01);
Out(FALC_GPC1, 0x60);
Out(FALC_CMDR2, 0x00);
/* Transmit pulse mask 0-2. */
Out(FALC_XPM0, 0x7D);
Out(FALC_XPM1, 0xAB);
Out(FALC_XPM2, 0x01);
/* Pulse count detection:
LOS detection after 176
consecutive 0s. */
Out(FALC_PCD , 0x0A);
/* Pulse count recovery:
LOS recovery after 22
consecutive 1s. */
Out(FALC_PCR , 0x15);
/* Interrupt mask register 2-4:
enable all IMR2 interrupts,
enable ES and SEC interrupts,
enable all IMR4 interrupts. */
Out(FALC_IMR2, 0x00);
Out(FALC_IMR3, In(FALC_IMR3) & ~0xC0);
Out(FALC_IMR4, 0x00);
/* Command register:
receiver, transmitter and
signalling transmitter reset. */
Out(FALC_CMDR, 0x51);
break;
case INTF_E1_PCM_PLE:
/* SIC1: Set data clock and data rate
(second part in FALC_FMR1).
PC6: Select frequency at CLK1 */
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_4MHZ)
{
Out(FALC_SIC1, 0x08);
Out(FALC_PC6, 0x02);
}
else
{
Out(FALC_SIC1, 0x00);
Out(FALC_PC6, 0x01);
}
/* /SYPR output, /SYPX input */
Out(FALC_PC1, 0x10);
/* /SCLKR output */
Out(FALC_PC5, 0x33);
/* receive clock system sourced by
DCO-R, transmit clock system
sourced by /SYPX */
Out(FALC_CMR2, 0x0C);
/* RCLK recovered from DCO-R */
Out(FALC_CMR1, 0x20);
Out(FALC_GPC1, 0x60);
Out(FALC_CMDR2,0x00);
/* Transmit pulse mask 0-2:
pulse shape programming for
R1=1.80 Ohm, additional
protection resistor=5.60 Ohm,
3V pulse level at the line. */
Out(FALC_XPM0, 0xB5);
Out(FALC_XPM1, 0x02);
Out(FALC_XPM2, 0x00);
/* Transmit service word pulse:
spare and Y bits fixed to 1. */
Out(FALC_XSW, 0x9F);
/* Frame mode register 0:
transmit and receive code
is HDB3 Code. */
Out(FALC_FMR0, 0xF0);
/* Frame mode register 1:
trans. CRC4 multiframe format,
latch error counter every sec
System interface mode
is 2Mbit/s. */
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_2MHZ)
{
Out(FALC_FMR1, 0x4C);
Out(FALC_SIC3, 0x04);
}
/* System interface mode
is 4Mbit/s. */
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_4MHZ)
{
Out(FALC_FMR1, 0x4E);
Out(FALC_SIC3, 0x00);
}
/* Frame mode register 2:
recei. NO!! CRC4 multiframe format,
automatic remote alarm,
automatic loss of multiframe. */
Out(FALC_FMR2, 0x83);
/* Interrupt port configuration:
push/pull output, active low.
SYNC freq = 2 MHz */
Out(FALC_IPC, 0x05);
/* Line interface mode 0:
master mode/slave mode */
Out(FALC_LIM0, 0x00);
/* Line interface mode 1:
receive input threshold 0.62V. */
Out(FALC_LIM1, 0x30);
/* Pulse count detection:
LOS detection after 176
consecutive 0s. */
Out(FALC_PCD , 0x0A);
/* Pulse count recovery:
LOS recovery after 22
consecutive 1s. */
Out(FALC_PCR , 0x15);
/* Transmit spare bits:
E bit is 1 in async state,
automatic trans of E bits,
spare bit fixed to 1. */
Out(FALC_XSP , 0x1C);
/* Transmit control 0+1:
timeslot 0 is starting with
SYPQ in transmit direction.
!!! Adapt to board !!! */
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_2MHZ)
{
/* Transmit counter offset
is 6 (PCM clock 2 MHz). */
Out(FALC_XC0 , 0x07);
Out(FALC_XC1 , 0x03);
}
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_4MHZ)
{
/* Transmit counter offset
is 3 (PCM clock 4 MHz). */
Out(FALC_XC0 , 0x02);
Out(FALC_XC1 , 0x03);
}
/* Receive control 0+1:
timeslot 0 is starting with
SYPQ in receive direction.
!!! Adapt to board !!! */
Out(FALC_RC0, 0x84);
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_4MHZ)
{
Out(FALC_RC1, 0x05);
}
else
{
Out(FALC_RC1, 0x04);
}
/* Interrupt mask register 2-4:
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