📄 falc.c
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/*******************************************************************************
Copyright (c) 2000, Infineon Technologies. All rights reserved.
No Warranty
Because the program is licensed free of charge, there is no warranty for
the program, to the extent permitted by applicable law. Except when
otherwise stated in writing the copyright holders and/or other parties
provide the program "as is" without warranty of any kind, either
expressed or implied, including, but not limited to, the implied
warranties of merchantability and fitness for a particular purpose. The
entire risk as to the quality and performance of the program is with
you. should the program prove defective, you assume the cost of all
necessary servicing, repair or correction.
In no event unless required by applicable law or agreed to in writing
will any copyright holder, or any other party who may modify and/or
redistribute the program as permitted above, be liable to you for
damages, including any general, special, incidental or consequential
damages arising out of the use or inability to use the program
(including but not limited to loss of data or data being rendered
inaccurate or losses sustained by you or third parties or a failure of
the program to operate with any other programs), even if such holder or
other party has been advised of the possibility of such damages.
*******************************************************************************
Module: FALC
Product ID: 22622.1.0.1
Version ID: 0.11.0.2
Description: Contains FALC access.
******************************************************************************/
// Group= FALC
/* ============================= */
/* Includes */
/* ============================= */
#include <stdio.h>
#include <absacc.h>
#include "sysdef.h"
#include "dds.h"
#include "sysvar.h"
#include "sysfunc.h"
#include "modid.h"
/* ============================= */
/* Local Macros & Definitions */
/* ============================= */
/* ============================= */
/* Local variable definition */
/* ============================= */
/* ============================= */
/* Local function declaration */
/* ============================= */
/* ============================= */
/* Global function definition */
/* ============================= */
/*******************************************************************************
Description:
Inititialization function of the FALC module.
Arguments:
NONE.
Return:
NONE.
Remarks:
This function initializes the FALC according to the
board configuration settings.
******************************************************************************/
void Falc_Init (void)
{
/* Adaption for oscillator 12,36MHz
according data sheet. */
Out(FALC_GCM1, 0xF0);
Out(FALC_GCM2, 0x51);
Out(FALC_GCM3, 0x00);
Out(FALC_GCM4, 0x80);
Out(FALC_GCM5, 0x07);
Out(FALC_GCM6, 0x15);
/* Do interface dependent settings. */
switch(G_Eeprom[CONFIG_INTF])
{
case INTF_E1_PCM_SYN:
case INTF_E1_PCM_PLE_TEST:
/* SIC1: Set data clock and data rate
(second part in FALC_FMR1).
PC6: Select frequency at CLK1 */
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_4MHZ)
{
Out(FALC_SIC1, 0x08);
Out(FALC_PC6, 0x02);
}
else
{
Out(FALC_SIC1, 0x00);
Out(FALC_PC6, 0x01);
}
/* Set characteristic of data path A. */
if (G_Eeprom[CONFIG_MODE] == MODE_COT_EXT)
{
/* RFM output, /SYPX input */
Out(FALC_PC1, 0x10);
/* /SCLKR output */
Out(FALC_PC5, 0x33);
/* internal clock system sourced by
DCO-R */
Out(FALC_CMR2, 0x0F);
}
else
{
/* /SYPR input, /SYPX input */
Out(FALC_PC1, 0x00);
/* /SCLKR output */
Out(FALC_PC5, 0x31);
/* internal clock system sourced by
/SYPR */
Out(FALC_CMR2, 0x00);
/* RCLK recovered from DCO-R */
Out(FALC_CMR1, 0x20);
}
Out(FALC_GPC1, 0x60);
Out(FALC_CMDR2, 0x00);
/* Interrupt port configuration:
push/pull output, active low.
SYNC freq = 8 kHz */
Out(FALC_IPC, 0x05);
/* Transmit pulse mask 0-2:
pulse shape programming for
R1=1.80 Ohm, additional
protection resistor=5.60 Ohm,
3V pulse level at the line. */
Out(FALC_XPM0, 0xB5);
Out(FALC_XPM1, 0x02);
Out(FALC_XPM2, 0x00);
/* Transmit service word pulse:
spare and Y bits fixed to 1. */
Out(FALC_XSW , 0x9F);
/* Frame mode register 0:
transmit and receive code
is HDB3 Code. */
Out(FALC_FMR0, 0xF0);
/* Frame mode register 1:
trans. CRC4 multiframe format,
latch error counter every sec
System interface mode
is 2Mbit/s. */
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_2MHZ)
{
Out(FALC_FMR1, 0x4C);
Out(FALC_SIC3, 0x04);
}
/* System interface mode
is 4Mbit/s. */
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_4MHZ)
{
Out(FALC_FMR1, 0x4E);
Out(FALC_SIC3, 0x00);
}
/* Frame mode register 2:
recei. NO!! CRC4 multiframe format,
automatic remote alarm,
automatic loss of multiframe. */
Out(FALC_FMR2, 0x83);
if (G_Eeprom[CONFIG_MODE] == MODE_COT_EXT)
{
/* Interrupt port configuration:
push/pull output, active low.
SYNC freq = 8 kHz */
Out(FALC_IPC, 0x01);
/* Line interface mode 0:
master mode/slave mode */
Out(FALC_LIM0, 0x00);
}
else
{
/* Interrupt port configuration:
push/pull output, active low.
SYNC freq = 2 MHz */
Out(FALC_IPC, 0x05);
/* Line interface mode 0:
master mode/slave mode */
Out(FALC_LIM0, 0x01);
}
/* Line interface mode 1:
receive input threshold 0.62V. */
Out(FALC_LIM1, 0x30);
/* Pulse count detection:
LOS detection after 176
consecutive 0s. */
Out(FALC_PCD , 0x0A);
/* Pulse count recovery:
LOS recovery after 22
consecutive 1s. */
Out(FALC_PCR , 0x15);
/* Transmit spare bits:
E bit is 1 in async state,
automatic trans of E bits,
spare bit fixed to 1. */
Out(FALC_XSP , 0x1C);
/* Transmit control 0+1:
timeslot 0 is starting with
SYPQ in transmit direction.
!!! Adapt to board !!! */
if (G_Eeprom[CONFIG_MODE] == MODE_COT_EXT)
{
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_2MHZ)
{
/* Transmit counter offset
is 6 (PCM clock 2 MHz). */
Out(FALC_XC0 , 0x07);
Out(FALC_XC1 , 0x04);
}
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_4MHZ)
{
/* Transmit counter offset
is 3 (PCM clock 4 MHz). */
Out(FALC_XC0 , 0x02);
Out(FALC_XC1 , 0x04);
}
}
else
{
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_2MHZ)
{
/* Transmit counter offset
is 6 (PCM clock 2 MHz). */
Out(FALC_XC0 , 0x07);
Out(FALC_XC1 , 0x03);
}
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_4MHZ)
{
/* Transmit counter offset
is 3 (PCM clock 4 MHz). */
Out(FALC_XC0 , 0x02);
Out(FALC_XC1 , 0x03);
}
}
/* Receive control 0+1:
timeslot 0 is starting with
SYPQ in receive direction.
!!! Adapt to board !!! */
Out(FALC_RC0, 0x84);
if (G_Eeprom[CONFIG_MODE] == MODE_COT_EXT)
{
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_4MHZ)
{
Out(FALC_RC1, 0x05);
}
else
{
Out(FALC_RC1, 0x04);
}
}
else
{
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_4MHZ)
{
Out(FALC_RC1, 0x04);
}
else
{
Out(FALC_RC1, 0x04);
}
}
/* Interrupt mask register 2-4:
enable all IMR2 interrupts,
enable ES and SEC interrupts,
enable all IMR4 interrupts. */
Out(FALC_IMR2, 0x00);
Out(FALC_IMR3, In(FALC_IMR3) & ~0xC0);
Out(FALC_IMR4, 0x00);
/* Command register:
receiver, transmitter and
signalling transmitter reset. */
Out(FALC_CMDR, 0x51);
break;
case INTF_T1_PCM_SYN:
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_4MHZ)
{
/* SIC1: Set data clock and data rate
(second part in FALC_FMR1).
PC6: Select frequency at CLK1 */
Out(FALC_SIC1, 0x0A);
Out(FALC_PC6, 0x02);
/* System interface mode
is 4Mbit/s. */
Out(FALC_FMR1, 0x9A);
}
if (G_Eeprom[CONFIG_P_CLK] == P_CLK_2MHZ)
{
/* SIC1: Transmit Buffer Size:
2 frames */
Out(FALC_SIC1, 0x02);
Out(FALC_PC6, 0x01);
/* Frame mode register 1:
PCM 24 mode,
CRC6 enabled,
System interface mode
is 2Mbit/s. */
Out(FALC_FMR1, 0x98);
Out(FALC_SIC3, 0x04);
}
/* Frame mode register 0:
transmit and receive code
is B8ZS Code. */
Out(FALC_FMR0, 0xF0);
/* Frame mode register 2:
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