📄 44binit.lst
字号:
HANDLER HandleZDMA0
57 000003A8
58 000003A8 HandlerZDMA0
59 000003A8 E24DD004 sub sp,sp,#4 ;decrement sp(to store jump
address)
60 000003AC E92D0001 stmfd sp!,{r0} ;PUSH the work register to s
tack(lr does't push because
it return to original addres
s)
61 000003B0 E59F0274 ldr r0,=HandleZDMA0 ;load the address of Han
dleXXX to r0
62 000003B4 E5900000 ldr r0,[r0] ;load the contents(service r
outine start address) of Han
dleXXX
63 000003B8 E58D0004 str r0,[sp,#4] ;store the contents(ISR) of
HandleXXX to stack
64 000003BC E8BD8001 ldmfd sp!,{r0,pc} ;POP the work register and p
c(jump to ISR)
172 000003C0 HandlerTICK
HANDLER HandleTICK
57 000003C0
58 000003C0 HandlerTICK
59 000003C0 E24DD004 sub sp,sp,#4 ;decrement sp(to store jump
address)
60 000003C4 E92D0001 stmfd sp!,{r0} ;PUSH the work register to s
tack(lr does't push because
it return to original addres
s)
61 000003C8 E59F0260 ldr r0,=HandleTICK ;load the address of Hand
leXXX to r0
62 000003CC E5900000 ldr r0,[r0] ;load the contents(service r
outine start address) of Han
ARM Macro Assembler Page 17
dleXXX
63 000003D0 E58D0004 str r0,[sp,#4] ;store the contents(ISR) of
HandleXXX to stack
64 000003D4 E8BD8001 ldmfd sp!,{r0,pc} ;POP the work register and p
c(jump to ISR)
173 000003D8 HandlerEINT4567
HANDLER HandleEINT4567
57 000003D8
58 000003D8 HandlerEINT4567
59 000003D8 E24DD004 sub sp,sp,#4 ;decrement sp(to store jump
address)
60 000003DC E92D0001 stmfd sp!,{r0} ;PUSH the work register to s
tack(lr does't push because
it return to original addres
s)
61 000003E0 E59F024C ldr r0,=HandleEINT4567 ;load the address of
HandleXXX to r0
62 000003E4 E5900000 ldr r0,[r0] ;load the contents(service r
outine start address) of Han
dleXXX
63 000003E8 E58D0004 str r0,[sp,#4] ;store the contents(ISR) of
HandleXXX to stack
64 000003EC E8BD8001 ldmfd sp!,{r0,pc} ;POP the work register and p
c(jump to ISR)
174 000003F0 HandlerEINT3
HANDLER HandleEINT3
57 000003F0
58 000003F0 HandlerEINT3
59 000003F0 E24DD004 sub sp,sp,#4 ;decrement sp(to store jump
address)
60 000003F4 E92D0001 stmfd sp!,{r0} ;PUSH the work register to s
tack(lr does't push because
it return to original addres
s)
61 000003F8 E59F0238 ldr r0,=HandleEINT3 ;load the address of Han
dleXXX to r0
62 000003FC E5900000 ldr r0,[r0] ;load the contents(service r
outine start address) of Han
dleXXX
63 00000400 E58D0004 str r0,[sp,#4] ;store the contents(ISR) of
HandleXXX to stack
64 00000404 E8BD8001 ldmfd sp!,{r0,pc} ;POP the work register and p
c(jump to ISR)
175 00000408 HandlerEINT2
HANDLER HandleEINT2
57 00000408
58 00000408 HandlerEINT2
59 00000408 E24DD004 sub sp,sp,#4 ;decrement sp(to store jump
address)
60 0000040C E92D0001 stmfd sp!,{r0} ;PUSH the work register to s
tack(lr does't push because
it return to original addres
s)
61 00000410 E59F0224 ldr r0,=HandleEINT2 ;load the address of Han
dleXXX to r0
62 00000414 E5900000 ldr r0,[r0] ;load the contents(service r
outine start address) of Han
dleXXX
63 00000418 E58D0004 str r0,[sp,#4] ;store the contents(ISR) of
ARM Macro Assembler Page 18
HandleXXX to stack
64 0000041C E8BD8001 ldmfd sp!,{r0,pc} ;POP the work register and p
c(jump to ISR)
176 00000420 HandlerEINT1
HANDLER HandleEINT1
57 00000420
58 00000420 HandlerEINT1
59 00000420 E24DD004 sub sp,sp,#4 ;decrement sp(to store jump
address)
60 00000424 E92D0001 stmfd sp!,{r0} ;PUSH the work register to s
tack(lr does't push because
it return to original addres
s)
61 00000428 E59F0210 ldr r0,=HandleEINT1 ;load the address of Han
dleXXX to r0
62 0000042C E5900000 ldr r0,[r0] ;load the contents(service r
outine start address) of Han
dleXXX
63 00000430 E58D0004 str r0,[sp,#4] ;store the contents(ISR) of
HandleXXX to stack
64 00000434 E8BD8001 ldmfd sp!,{r0,pc} ;POP the work register and p
c(jump to ISR)
177 00000438 HandlerEINT0
HANDLER HandleEINT0
57 00000438
58 00000438 HandlerEINT0
59 00000438 E24DD004 sub sp,sp,#4 ;decrement sp(to store jump
address)
60 0000043C E92D0001 stmfd sp!,{r0} ;PUSH the work register to s
tack(lr does't push because
it return to original addres
s)
61 00000440 E59F01FC ldr r0,=HandleEINT0 ;load the address of Han
dleXXX to r0
62 00000444 E5900000 ldr r0,[r0] ;load the contents(service r
outine start address) of Han
dleXXX
63 00000448 E58D0004 str r0,[sp,#4] ;store the contents(ISR) of
HandleXXX to stack
64 0000044C E8BD8001 ldmfd sp!,{r0,pc} ;POP the work register and p
c(jump to ISR)
178 00000450
179 00000450
180 00000450 ;One of the following two routines can be used for non-v
ectored interrupt.
181 00000450
182 00000450 IsrIRQ ;using I_ISPR register.
183 00000450 E24DD004 sub sp,sp,#4 ;reserved for PC
184 00000454 E92D0300 stmfd sp!,{r8-r9}
185 00000458
186 00000458 ;IMPORTANT CAUTION
187 00000458 ;if I_ISPC isn't used properly, I_ISPR can be 0 in this
routine.
188 00000458
189 00000458 E59F91E8 ldr r9,=I_ISPR
190 0000045C E5999000 ldr r9,[r9]
191 00000460 E3A08000 mov r8,#0x0
192 00000464 0
193 00000464 E1B090A9 movs r9,r9,lsr #1
ARM Macro Assembler Page 19
194 00000468 2A000001 bcs %F1
195 0000046C E2888004 add r8,r8,#4
196 00000470 EAFFFFFB b %B0
197 00000474
198 00000474 1
199 00000474 E59F9164 ldr r9,=HandleADC
200 00000478 E0899008 add r9,r9,r8
201 0000047C E5999000 ldr r9,[r9]
202 00000480 E58D9008 str r9,[sp,#8]
203 00000484 E8BD8300 ldmfd sp!,{r8-r9,pc}
204 00000488
205 00000488
206 00000488 ;****************************************************
207 00000488 ;* START *
208 00000488 ;****************************************************
209 00000488 ResetHandler
210 00000488 E59F01C0 ldr r0,=WTCON ;watch dog disable
211 0000048C E3A01000 ldr r1,=0x0
212 00000490 E5801000 str r1,[r0]
213 00000494
214 00000494 E59F01B8 ldr r0,=INTMSK
215 00000498 E3E0133E ldr r1,=0x07ffffff ;all interrupt disable
216 0000049C E5801000 str r1,[r0]
217 000004A0
218 000004A0 ;****************************************************
219 000004A0 ;* Set clock control registers *
220 000004A0 ;****************************************************
221 000004A0 E59F01B0 ldr r0,=LOCKTIME
222 000004A4 E3A01E32 ldr r1,=800 ; count = t_lock * Fin (t_lo
ck=200us, Fin=4MHz) = 800
223 000004A8 E5801000 str r1,[r0]
224 000004AC
225 000004AC [ PLLONSTART
226 000004AC E3A00776 ldr r0,=PLLCON ;temporary setting of PLL
227 000004B0 E59F11A4 ldr r1,=((M_DIV<<12)+(P_DIV<<4)+S_DIV)
;Fin=10MHz,Fout=40MHz
228 000004B4 E5801000 str r1,[r0]
229 000004B8 ]
230 000004B8
231 000004B8 E59F01A0 ldr r0,=CLKCON
232 000004BC E59F11A0 ldr r1,=0x7ff8 ;All unit block CLK enable
233 000004C0 E5801000 str r1,[r0]
234 000004C4
235 000004C4 ;****************************************************
236 000004C4 ;* Set memory control registers *
237 000004C4 ;****************************************************
238 000004C4 E59F0180 ldr r0,=SMRDATA
239 000004C8 E8903FFE ldmia r0,{r1-r13}
240 000004CC E3A00772 ldr r0,=0x01c80000 ;BWSCON Address
241 000004D0 E8803FFE stmia r0,{r1-r13}
242 000004D4
243 000004D4 ;****************************************************
244 000004D4 ;* Initialize stacks *
245 000004D4 ;****************************************************
246 000004D4 E59FD18C ldr sp, =SVCStack ;Why?
247 000004D8 EB000012 bl InitStacks
248 000004DC
249 000004DC ;****************************************************
250 000004DC ;* Setup IRQ handler *
ARM Macro Assembler Page 20
251 000004DC ;****************************************************
252 000004DC E59F00E8 ldr r0,=HandleIRQ ;This routine is needed
253 000004E0 E59F118C ldr r1,=IsrIRQ ;if there isn't 'subs pc,lr,
#4' at 0x18, 0x1c
254 000004E4 E5801000 str r1,[r0]
255 000004E8
256 000004E8 ;*******************************************************
*
257 000004E8 ;* Copy and paste RW data/zero initialized data *
258 000004E8 ;*******************************************************
*
259 000004E8 E59F0188 LDR r0, =|Image$$RO$$Limit|
; Get pointer to ROM data
260 000004EC E59F1188 LDR r1, =|Image$$RW$$Base| ; and RAM copy
261 000004F0 E59F3188 LDR r3, =|Image$$ZI$$Base|
262 000004F4 ;Zero init base =>⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -