📄 stm32f0xx.h
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__IO uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
__IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
__IO uint32_t IOGXCR[6]; /*!< TSC I/O group x counter register, Address offset: 0x34-48 */
} TSC_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
__IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
uint16_t RESERVED1; /*!< Reserved, 0x0E */
__IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
uint16_t RESERVED2; /*!< Reserved, 0x12 */
__IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
__IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
uint16_t RESERVED3; /*!< Reserved, 0x1A */
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
__IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
uint16_t RESERVED4; /*!< Reserved, 0x26 */
__IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
uint16_t RESERVED5; /*!< Reserved, 0x2A */
} USART_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
/*!< Peripheral memory map */
#define APBPERIPH_BASE PERIPH_BASE
#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
#define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
#define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define CEC ((CEC_TypeDef *) CEC_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define COMP ((COMP_TypeDef *) COMP_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define OB ((OB_TypeDef *) OB_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define TSC ((TSC_TypeDef *) TSC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers Bits Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Analog to Digital Converter (ADC) */
/* */
/******************************************************************************/
/******************** Bits definition for ADC_ISR register ******************/
#define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
/* Old EOSEQ bit definition, maintained for legacy purpose */
#define ADC_ISR_EOS ADC_ISR_EOSEQ
/******************** Bits definition for ADC_IER register ******************/
#define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
#define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
#define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
/* Old EOSEQIE bit definition, maintained for legacy purpose */
#define ADC_IER_EOSIE ADC_IER_EOSEQIE
/******************** Bits definition for ADC_CR register *******************/
#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
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