📄 stm32f0xx.h
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__IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
__IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
uint16_t RESERVED3; /*!< Reserved, 0x2A */
}GPIO_TypeDef;
/**
* @brief SysTem Configuration
*/
typedef struct
{
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
uint32_t RESERVED; /*!< Reserved, 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
} SYSCFG_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
__IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
__IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
__IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
__IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
__IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
__IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
}I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
} IWDG_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
__IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
} PWR_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
__IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
__IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
__IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
__IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
__IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
__IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
__IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
__IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
__IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
} RCC_TypeDef;
/**
* @brief Real-Time Clock
*/
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
__IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
__IO uint32_t CAL; /*!< RTC calibration register, Address offset: 0x3C */
__IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */
__IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
__IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
__IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
__IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
__IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
} RTC_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
typedef struct
{
__IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
uint16_t RESERVED0; /*!< Reserved, 0x02 */
__IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
uint16_t RESERVED2; /*!< Reserved, 0x0A */
__IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
uint16_t RESERVED3; /*!< Reserved, 0x0E */
__IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
uint16_t RESERVED4; /*!< Reserved, 0x12 */
__IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
uint16_t RESERVED5; /*!< Reserved, 0x16 */
__IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
uint16_t RESERVED6; /*!< Reserved, 0x1A */
__IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
uint16_t RESERVED7; /*!< Reserved, 0x1E */
__IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
uint16_t RESERVED8; /*!< Reserved, 0x22 */
} SPI_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
uint16_t RESERVED0; /*!< Reserved, 0x02 */
__IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint16_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
uint16_t RESERVED2; /*!< Reserved, 0x0A */
__IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
uint16_t RESERVED3; /*!< Reserved, 0x0E */
__IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
uint16_t RESERVED4; /*!< Reserved, 0x12 */
__IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
uint16_t RESERVED5; /*!< Reserved, 0x16 */
__IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
uint16_t RESERVED6; /*!< Reserved, 0x1A */
__IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
uint16_t RESERVED7; /*!< Reserved, 0x1E */
__IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
uint16_t RESERVED8; /*!< Reserved, 0x22 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint16_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
uint16_t RESERVED10; /*!< Reserved, 0x2A */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
uint16_t RESERVED12; /*!< Reserved, 0x32 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
uint16_t RESERVED17; /*!< Reserved, 0x26 */
__IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
uint16_t RESERVED18; /*!< Reserved, 0x4A */
__IO uint16_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
uint16_t RESERVED19; /*!< Reserved, 0x4E */
__IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
uint16_t RESERVED20; /*!< Reserved, 0x52 */
} TIM_TypeDef;
/**
* @brief Touch Sensing Controller (TSC)
*/
typedef struct
{
__IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
__IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
__IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
__IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
__IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
__IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
__IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
__IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
__IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
__IO uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
__IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
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