📄 stm32f0xx.h
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SPI1_IRQn = 25, /*!< SPI1 Interrupt */
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
USART1_IRQn = 27, /*!< USART1 Interrupt */
USART2_IRQn = 28, /*!< USART2 Interrupt */
CEC_IRQn = 30 /*!< CEC Interrupt */
} IRQn_Type;
/**
* @}
*/
#include "core_cm0.h"
#include "system_stm32f0xx.h"
#include <stdint.h>
/** @addtogroup Exported_types
* @{
*/
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
__IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
__IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
__IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
__IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
__IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
uint32_t RESERVED1; /*!< Reserved, 0x18 */
uint32_t RESERVED2; /*!< Reserved, 0x1C */
__IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
uint32_t RESERVED3; /*!< Reserved, 0x24 */
__IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
__IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CCR;
} ADC_Common_TypeDef;
/**
* @brief HDMI-CEC
*/
typedef struct
{
__IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
__IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
__IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
__IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
__IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
__IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
}CEC_TypeDef;
/**
* @brief Comparator
*/
typedef struct
{
__IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */
} COMP_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
uint8_t RESERVED0; /*!< Reserved, 0x05 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED2; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
} CRC_TypeDef;
/**
* @brief Digital to Analog Converter
*/
typedef struct
{
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
uint32_t RESERVED[6]; /*!< Reserved, 0x14 */
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
uint32_t RESERVED1; /*!< Reserved, 0x30 */
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
} DAC_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
}DBGMCU_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA channel x configuration register */
__IO uint32_t CNDTR; /*!< DMA channel x number of data register */
__IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
__IO uint32_t CMAR; /*!< DMA channel x memory address register */
} DMA_Channel_TypeDef;
typedef struct
{
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
__IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
__IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
__IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
__IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
__IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
}EXTI_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
__IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
__IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
__IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
__IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
__IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
__IO uint32_t RESERVED; /*!< Reserved, 0x18 */
__IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
__IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
} FLASH_TypeDef;
/**
* @brief Option Bytes Registers
*/
typedef struct
{
__IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
__IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
uint16_t RESERVED0; /*!< Reserved, 0x04 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
__IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
} OB_TypeDef;
/**
* @brief General Purpose IO
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
uint16_t RESERVED0; /*!< Reserved, 0x06 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
uint16_t RESERVED1; /*!< Reserved, 0x12 */
__IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
uint16_t RESERVED2; /*!< Reserved, 0x16 */
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