📄 stm8s_tim1.ls
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3692 ; 1019 void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode)
3692 ; 1020 {
3693 switch .text
3694 045d _TIM1_CounterModeConfig:
3696 045d 88 push a
3697 00000000 OFST: set 0
3700 ; 1022 assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));
3702 ; 1026 TIM1->CR1 = (u8)((TIM1->CR1 & (u8)((u8)(~TIM1_CR1_CMS) & (u8)(~TIM1_CR1_DIR))) | (u8)TIM1_CounterMode);
3704 045e c65250 ld a,21072
3705 0461 a48f and a,#143
3706 0463 1a01 or a,(OFST+1,sp)
3707 0465 c75250 ld 21072,a
3708 ; 1027 }
3711 0468 84 pop a
3712 0469 81 ret
3770 ; 1038 void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3770 ; 1039 {
3771 switch .text
3772 046a _TIM1_ForcedOC1Config:
3774 046a 88 push a
3775 00000000 OFST: set 0
3778 ; 1041 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3780 ; 1044 TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3782 046b c65258 ld a,21080
3783 046e a48f and a,#143
3784 0470 1a01 or a,(OFST+1,sp)
3785 0472 c75258 ld 21080,a
3786 ; 1045 }
3789 0475 84 pop a
3790 0476 81 ret
3826 ; 1056 void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3826 ; 1057 {
3827 switch .text
3828 0477 _TIM1_ForcedOC2Config:
3830 0477 88 push a
3831 00000000 OFST: set 0
3834 ; 1059 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3836 ; 1062 TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3838 0478 c65259 ld a,21081
3839 047b a48f and a,#143
3840 047d 1a01 or a,(OFST+1,sp)
3841 047f c75259 ld 21081,a
3842 ; 1063 }
3845 0482 84 pop a
3846 0483 81 ret
3882 ; 1075 void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3882 ; 1076 {
3883 switch .text
3884 0484 _TIM1_ForcedOC3Config:
3886 0484 88 push a
3887 00000000 OFST: set 0
3890 ; 1078 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3892 ; 1081 TIM1->CCMR3 = (u8)((TIM1->CCMR3 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3894 0485 c6525a ld a,21082
3895 0488 a48f and a,#143
3896 048a 1a01 or a,(OFST+1,sp)
3897 048c c7525a ld 21082,a
3898 ; 1082 }
3901 048f 84 pop a
3902 0490 81 ret
3938 ; 1094 void TIM1_ForcedOC4Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3938 ; 1095 {
3939 switch .text
3940 0491 _TIM1_ForcedOC4Config:
3942 0491 88 push a
3943 00000000 OFST: set 0
3946 ; 1097 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3948 ; 1100 TIM1->CCMR4 = (u8)((TIM1->CCMR4 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3950 0492 c6525b ld a,21083
3951 0495 a48f and a,#143
3952 0497 1a01 or a,(OFST+1,sp)
3953 0499 c7525b ld 21083,a
3954 ; 1101 }
3957 049c 84 pop a
3958 049d 81 ret
3994 ; 1110 void TIM1_ARRPreloadConfig(FunctionalState NewState)
3994 ; 1111 {
3995 switch .text
3996 049e _TIM1_ARRPreloadConfig:
4000 ; 1113 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4002 ; 1116 if (NewState != DISABLE)
4004 049e 4d tnz a
4005 049f 2706 jreq L5502
4006 ; 1118 TIM1->CR1 |= TIM1_CR1_ARPE;
4008 04a1 721e5250 bset 21072,#7
4010 04a5 2004 jra L7502
4011 04a7 L5502:
4012 ; 1122 TIM1->CR1 &= (u8)(~TIM1_CR1_ARPE);
4014 04a7 721f5250 bres 21072,#7
4015 04ab L7502:
4016 ; 1124 }
4019 04ab 81 ret
4054 ; 1133 void TIM1_SelectCOM(FunctionalState NewState)
4054 ; 1134 {
4055 switch .text
4056 04ac _TIM1_SelectCOM:
4060 ; 1136 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4062 ; 1139 if (NewState != DISABLE)
4064 04ac 4d tnz a
4065 04ad 2706 jreq L7702
4066 ; 1141 TIM1->CR2 |= TIM1_CR2_COMS;
4068 04af 72145251 bset 21073,#2
4070 04b3 2004 jra L1012
4071 04b5 L7702:
4072 ; 1145 TIM1->CR2 &= (u8)(~TIM1_CR2_COMS);
4074 04b5 72155251 bres 21073,#2
4075 04b9 L1012:
4076 ; 1147 }
4079 04b9 81 ret
4115 ; 1155 void TIM1_CCPreloadControl(FunctionalState NewState)
4115 ; 1156 {
4116 switch .text
4117 04ba _TIM1_CCPreloadControl:
4121 ; 1158 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4123 ; 1161 if (NewState != DISABLE)
4125 04ba 4d tnz a
4126 04bb 2706 jreq L1212
4127 ; 1163 TIM1->CR2 |= TIM1_CR2_CCPC;
4129 04bd 72105251 bset 21073,#0
4131 04c1 2004 jra L3212
4132 04c3 L1212:
4133 ; 1167 TIM1->CR2 &= (u8)(~TIM1_CR2_CCPC);
4135 04c3 72115251 bres 21073,#0
4136 04c7 L3212:
4137 ; 1169 }
4140 04c7 81 ret
4176 ; 1178 void TIM1_OC1PreloadConfig(FunctionalState NewState)
4176 ; 1179 {
4177 switch .text
4178 04c8 _TIM1_OC1PreloadConfig:
4182 ; 1181 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4184 ; 1184 if (NewState != DISABLE)
4186 04c8 4d tnz a
4187 04c9 2706 jreq L3412
4188 ; 1186 TIM1->CCMR1 |= TIM1_CCMR_OCxPE;
4190 04cb 72165258 bset 21080,#3
4192 04cf 2004 jra L5412
4193 04d1 L3412:
4194 ; 1190 TIM1->CCMR1 &= (u8)(~TIM1_CCMR_OCxPE);
4196 04d1 72175258 bres 21080,#3
4197 04d5 L5412:
4198 ; 1192 }
4201 04d5 81 ret
4237 ; 1201 void TIM1_OC2PreloadConfig(FunctionalState NewState)
4237 ; 1202 {
4238 switch .text
4239 04d6 _TIM1_OC2PreloadConfig:
4243 ; 1204 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4245 ; 1207 if (NewState != DISABLE)
4247 04d6 4d tnz a
4248 04d7 2706 jreq L5612
4249 ; 1209 TIM1->CCMR2 |= TIM1_CCMR_OCxPE;
4251 04d9 72165259 bset 21081,#3
4253 04dd 2004 jra L7612
4254 04df L5612:
4255 ; 1213 TIM1->CCMR2 &= (u8)(~TIM1_CCMR_OCxPE);
4257 04df 72175259 bres 21081,#3
4258 04e3 L7612:
4259 ; 1215 }
4262 04e3 81 ret
4298 ; 1224 void TIM1_OC3PreloadConfig(FunctionalState NewState)
4298 ; 1225 {
4299 switch .text
4300 04e4 _TIM1_OC3PreloadConfig:
4304 ; 1227 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4306 ; 1230 if (NewState != DISABLE)
4308 04e4 4d tnz a
4309 04e5 2706 jreq L7022
4310 ; 1232 TIM1->CCMR3 |= TIM1_CCMR_OCxPE;
4312 04e7 7216525a bset 21082,#3
4314 04eb 2004 jra L1122
4315 04ed L7022:
4316 ; 1236 TIM1->CCMR3 &= (u8)(~TIM1_CCMR_OCxPE);
4318 04ed 7217525a bres 21082,#3
4319 04f1 L1122:
4320 ; 1238 }
4323 04f1 81 ret
4359 ; 1248 void TIM1_OC4PreloadConfig(FunctionalState NewState)
4359 ; 1249 {
4360 switch .text
4361 04f2 _TIM1_OC4PreloadConfig:
4365 ; 1251 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4367 ; 1254 if (NewState != DISABLE)
4369 04f2 4d tnz a
4370 04f3 2706 jreq L1322
4371 ; 1256 TIM1->CCMR4 |= TIM1_CCMR_OCxPE;
4373 04f5 7216525b bset 21083,#3
4375 04f9 2004 jra L3322
4376 04fb L1322:
4377 ; 1260 TIM1->CCMR4 &= (u8)(~TIM1_CCMR_OCxPE);
4379 04fb 7217525b bres 21083,#3
4380 04ff L3322:
4381 ; 1262 }
4384 04ff 81 ret
4419 ; 1270 void TIM1_OC1FastConfig(FunctionalState NewState)
4419 ; 1271 {
4420 switch .text
4421 0500 _TIM1_OC1FastConfig:
4425 ; 1273 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4427 ; 1276 if (NewState != DISABLE)
4429 0500 4d tnz a
4430 0501 2706 jreq L3522
4431 ; 1278 TIM1->CCMR1 |= TIM1_CCMR_OCxFE;
4433 0503 72145258 bset 21080,#2
4435 0507 2004 jra L5522
4436 0509 L3522:
4437 ; 1282 TIM1->CCMR1 &= (u8)(~TIM1_CCMR_OCxFE);
4439 0509 72155258 bres 21080,#2
4440 050d L5522:
4441 ; 1284 }
4444 050d 81 ret
4479 ; 1294 void TIM1_OC2FastConfig(FunctionalState NewState)
4479 ; 1295 {
4480 switch .text
4481 050e _TIM1_OC2FastConfig:
4485 ; 1297 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4487 ; 1300 if (NewState != DISABLE)
4489 050e 4d tnz a
4490 050f 2706 jreq L5722
4491 ; 1302 TIM1->CCMR2 |= TIM1_CCMR_OCxFE;
4493 0511 72145259 bset 21081,#2
4495 0515 2004 jra L7722
4496 0517 L5722:
4497 ; 1306 TIM1->CCMR2 &= (u8)(~TIM1_CCMR_OCxFE);
4499 0517 72155259 bres 21081,#2
4500 051b L7722:
4501 ; 1308 }
4504 051b 81 ret
4539 ; 1317 void TIM1_OC3FastConfig(FunctionalState NewState)
4539 ; 1318 {
4540 switch .text
4541 051c _TIM1_OC3FastConfig:
4545 ; 1320 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4547 ; 1323 if (NewState != DISABLE)
4549 051c 4d tnz a
4550 051d 2706 jreq L7132
4551 ; 1325 TIM1->CCMR3 |= TIM1_CCMR_OCxFE;
4553 051f 7214525a bset 21082,#2
4555 0523 2004 jra L1232
4556 0525 L7132:
4557 ; 1329 TIM1->CCMR3 &= (u8)(~TIM1_CCMR_OCxFE);
4559 0525 7215525a bres 21082,#2
4560 0529 L1232:
4561 ; 1331 }
4564 0529 81 ret
4599 ; 1340 void TIM1_OC4FastConfig(FunctionalState NewS⌨️ 快捷键说明
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