📄 stm8s_tim1.ls
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2596 036e c75253 ld 21075,a
2597 ; 694 }
2600 0371 85 popw x
2601 0372 81 ret
2690 ; 716 void TIM1_TIxExternalClockConfig(TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource,
2690 ; 717 TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
2690 ; 718 u8 ICFilter)
2690 ; 719 {
2691 switch .text
2692 0373 _TIM1_TIxExternalClockConfig:
2694 0373 89 pushw x
2695 00000000 OFST: set 0
2698 ; 721 assert_param(IS_TIM1_TIXCLK_SOURCE_OK(TIM1_TIxExternalCLKSource));
2700 ; 722 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
2702 ; 723 assert_param(IS_TIM1_IC_FILTER_OK(ICFilter));
2704 ; 726 if (TIM1_TIxExternalCLKSource == TIM1_TIXEXTERNALCLK1SOURCE_TI2)
2706 0374 9e ld a,xh
2707 0375 a160 cp a,#96
2708 0377 260f jrne L1131
2709 ; 728 TI2_Config((u8)TIM1_ICPolarity, (u8)TIM1_ICSELECTION_DIRECTTI, (u8)ICFilter);
2711 0379 7b05 ld a,(OFST+5,sp)
2712 037b 88 push a
2713 037c ae0001 ldw x,#1
2714 037f 7b03 ld a,(OFST+3,sp)
2715 0381 95 ld xh,a
2716 0382 cd0845 call L5_TI2_Config
2718 0385 84 pop a
2720 0386 200d jra L3131
2721 0388 L1131:
2722 ; 732 TI1_Config((u8)TIM1_ICPolarity, (u8)TIM1_ICSELECTION_DIRECTTI, (u8)ICFilter);
2724 0388 7b05 ld a,(OFST+5,sp)
2725 038a 88 push a
2726 038b ae0001 ldw x,#1
2727 038e 7b03 ld a,(OFST+3,sp)
2728 0390 95 ld xh,a
2729 0391 cd0815 call L3_TI1_Config
2731 0394 84 pop a
2732 0395 L3131:
2733 ; 736 TIM1_SelectInputTrigger(TIM1_TIxExternalCLKSource);
2735 0395 7b01 ld a,(OFST+1,sp)
2736 0397 ad0a call _TIM1_SelectInputTrigger
2738 ; 739 TIM1->SMCR |= (u8)(TIM1_SLAVEMODE_EXTERNAL1);
2740 0399 c65252 ld a,21074
2741 039c aa07 or a,#7
2742 039e c75252 ld 21074,a
2743 ; 740 }
2746 03a1 85 popw x
2747 03a2 81 ret
2832 ; 752 void TIM1_SelectInputTrigger(TIM1_TS_TypeDef TIM1_InputTriggerSource)
2832 ; 753 {
2833 switch .text
2834 03a3 _TIM1_SelectInputTrigger:
2836 03a3 88 push a
2837 00000000 OFST: set 0
2840 ; 755 assert_param(IS_TIM1_TRIGGER_SELECTION_OK(TIM1_InputTriggerSource));
2842 ; 758 TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(~TIM1_SMCR_TS)) | (u8)TIM1_InputTriggerSource);
2844 03a4 c65252 ld a,21074
2845 03a7 a48f and a,#143
2846 03a9 1a01 or a,(OFST+1,sp)
2847 03ab c75252 ld 21074,a
2848 ; 759 }
2851 03ae 84 pop a
2852 03af 81 ret
2888 ; 769 void TIM1_UpdateDisableConfig(FunctionalState NewState)
2888 ; 770 {
2889 switch .text
2890 03b0 _TIM1_UpdateDisableConfig:
2894 ; 772 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2896 ; 775 if (NewState != DISABLE)
2898 03b0 4d tnz a
2899 03b1 2706 jreq L1731
2900 ; 777 TIM1->CR1 |= TIM1_CR1_UDIS;
2902 03b3 72125250 bset 21072,#1
2904 03b7 2004 jra L3731
2905 03b9 L1731:
2906 ; 781 TIM1->CR1 &= (u8)(~TIM1_CR1_UDIS);
2908 03b9 72135250 bres 21072,#1
2909 03bd L3731:
2910 ; 783 }
2913 03bd 81 ret
2971 ; 793 void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
2971 ; 794 {
2972 switch .text
2973 03be _TIM1_UpdateRequestConfig:
2977 ; 796 assert_param(IS_TIM1_UPDATE_SOURCE_OK(TIM1_UpdateSource));
2979 ; 799 if (TIM1_UpdateSource != TIM1_UPDATESOURCE_GLOBAL)
2981 03be 4d tnz a
2982 03bf 2706 jreq L3241
2983 ; 801 TIM1->CR1 |= TIM1_CR1_URS;
2985 03c1 72145250 bset 21072,#2
2987 03c5 2004 jra L5241
2988 03c7 L3241:
2989 ; 805 TIM1->CR1 &= (u8)(~TIM1_CR1_URS);
2991 03c7 72155250 bres 21072,#2
2992 03cb L5241:
2993 ; 807 }
2996 03cb 81 ret
3032 ; 816 void TIM1_SelectHallSensor(FunctionalState NewState)
3032 ; 817 {
3033 switch .text
3034 03cc _TIM1_SelectHallSensor:
3038 ; 819 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
3040 ; 822 if (NewState != DISABLE)
3042 03cc 4d tnz a
3043 03cd 2706 jreq L5441
3044 ; 824 TIM1->CR2 |= TIM1_CR2_TI1S;
3046 03cf 721e5251 bset 21073,#7
3048 03d3 2004 jra L7441
3049 03d5 L5441:
3050 ; 828 TIM1->CR2 &= (u8)(~TIM1_CR2_TI1S);
3052 03d5 721f5251 bres 21073,#7
3053 03d9 L7441:
3054 ; 830 }
3057 03d9 81 ret
3114 ; 841 void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode)
3114 ; 842 {
3115 switch .text
3116 03da _TIM1_SelectOnePulseMode:
3120 ; 844 assert_param(IS_TIM1_OPM_MODE_OK(TIM1_OPMode));
3122 ; 847 if (TIM1_OPMode != TIM1_OPMODE_REPETITIVE)
3124 03da 4d tnz a
3125 03db 2706 jreq L7741
3126 ; 849 TIM1->CR1 |= TIM1_CR1_OPM;
3128 03dd 72165250 bset 21072,#3
3130 03e1 2004 jra L1051
3131 03e3 L7741:
3132 ; 853 TIM1->CR1 &= (u8)(~TIM1_CR1_OPM);
3134 03e3 72175250 bres 21072,#3
3135 03e7 L1051:
3136 ; 856 }
3139 03e7 81 ret
3237 ; 872 void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
3237 ; 873 {
3238 switch .text
3239 03e8 _TIM1_SelectOutputTrigger:
3241 03e8 88 push a
3242 00000000 OFST: set 0
3245 ; 876 assert_param(IS_TIM1_TRGO_SOURCE_OK(TIM1_TRGOSource));
3247 ; 878 TIM1->CR2 = (u8)((TIM1->CR2 & (u8)(~TIM1_CR2_MMS )) | (u8) TIM1_TRGOSource);
3249 03e9 c65251 ld a,21073
3250 03ec a48f and a,#143
3251 03ee 1a01 or a,(OFST+1,sp)
3252 03f0 c75251 ld 21073,a
3253 ; 879 }
3256 03f3 84 pop a
3257 03f4 81 ret
3331 ; 891 void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
3331 ; 892 {
3332 switch .text
3333 03f5 _TIM1_SelectSlaveMode:
3335 03f5 88 push a
3336 00000000 OFST: set 0
3339 ; 895 assert_param(IS_TIM1_SLAVE_MODE_OK(TIM1_SlaveMode));
3341 ; 898 TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(~TIM1_SMCR_SMS)) | (u8)TIM1_SlaveMode);
3343 03f6 c65252 ld a,21074
3344 03f9 a4f8 and a,#248
3345 03fb 1a01 or a,(OFST+1,sp)
3346 03fd c75252 ld 21074,a
3347 ; 900 }
3350 0400 84 pop a
3351 0401 81 ret
3387 ; 908 void TIM1_SelectMasterSlaveMode(FunctionalState NewState)
3387 ; 909 {
3388 switch .text
3389 0402 _TIM1_SelectMasterSlaveMode:
3393 ; 911 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
3395 ; 914 if (NewState != DISABLE)
3397 0402 4d tnz a
3398 0403 2706 jreq L3161
3399 ; 916 TIM1->SMCR |= TIM1_SMCR_MSM;
3401 0405 721e5252 bset 21074,#7
3403 0409 2004 jra L5161
3404 040b L3161:
3405 ; 920 TIM1->SMCR &= (u8)(~TIM1_SMCR_MSM);
3407 040b 721f5252 bres 21074,#7
3408 040f L5161:
3409 ; 922 }
3412 040f 81 ret
3498 ; 944 void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode,
3498 ; 945 TIM1_ICPolarity_TypeDef TIM1_IC1Polarity,
3498 ; 946 TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
3498 ; 947 {
3499 switch .text
3500 0410 _TIM1_EncoderInterfaceConfig:
3502 0410 89 pushw x
3503 00000000 OFST: set 0
3506 ; 951 assert_param(IS_TIM1_ENCODER_MODE_OK(TIM1_EncoderMode));
3508 ; 952 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC1Polarity));
3510 ; 953 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC2Polarity));
3512 ; 956 if (TIM1_IC1Polarity != TIM1_ICPOLARITY_RISING)
3514 0411 9f ld a,xl
3515 0412 4d tnz a
3516 0413 2706 jreq L7561
3517 ; 958 TIM1->CCER1 |= TIM1_CCER1_CC1P;
3519 0415 7212525c bset 21084,#1
3521 0419 2004 jra L1661
3522 041b L7561:
3523 ; 962 TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC1P);
3525 041b 7213525c bres 21084,#1
3526 041f L1661:
3527 ; 965 if (TIM1_IC2Polarity != TIM1_ICPOLARITY_RISING)
3529 041f 0d05 tnz (OFST+5,sp)
3530 0421 2706 jreq L3661
3531 ; 967 TIM1->CCER1 |= TIM1_CCER1_CC2P;
3533 0423 721a525c bset 21084,#5
3535 0427 2004 jra L5661
3536 0429 L3661:
3537 ; 971 TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC2P);
3539 0429 721b525c bres 21084,#5
3540 042d L5661:
3541 ; 974 TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(TIM1_SMCR_MSM | TIM1_SMCR_TS)) | (u8) TIM1_EncoderMode);
3543 042d c65252 ld a,21074
3544 0430 a4f0 and a,#240
3545 0432 1a01 or a,(OFST+1,sp)
3546 0434 c75252 ld 21074,a
3547 ; 977 TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_CCxS)) | (u8) CCMR_TIxDirect_Set);
3549 0437 c65258 ld a,21080
3550 043a a4fc and a,#252
3551 043c aa01 or a,#1
3552 043e c75258 ld 21080,a
3553 ; 978 TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_CCxS)) | (u8) CCMR_TIxDirect_Set);
3555 0441 c65259 ld a,21081
3556 0444 a4fc and a,#252
3557 0446 aa01 or a,#1
3558 0448 c75259 ld 21081,a
3559 ; 980 }
3562 044b 85 popw x
3563 044c 81 ret
3630 ; 993 void TIM1_PrescalerConfig(u16 Prescaler,
3630 ; 994 TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
3630 ; 995 {
3631 switch .text
3632 044d _TIM1_PrescalerConfig:
3634 044d 89 pushw x
3635 00000000 OFST: set 0
3638 ; 997 assert_param(IS_TIM1_PRESCALER_RELOAD_OK(TIM1_PSCReloadMode));
3640 ; 1000 TIM1->PSCRH = (u8)(Prescaler >> 8);
3642 044e 9e ld a,xh
3643 044f c75260 ld 21088,a
3644 ; 1001 TIM1->PSCRL = (u8)(Prescaler);
3646 0452 9f ld a,xl
3647 0453 c75261 ld 21089,a
3648 ; 1004 TIM1->EGR = (u8)TIM1_PSCReloadMode;
3650 0456 7b05 ld a,(OFST+5,sp)
3651 0458 c75257 ld 21079,a
3652 ; 1006 }
3655 045b 85 popw x
3656 045c 81 ret
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