📄 stm8s_tim1.ls
字号:
853 016a 7b09 ld a,(OFST+6,sp)
854 016c c75267 ld 21095,a
855 ; 224 TIM1->CCR2L = (u8)(TIM1_Pulse);
857 016f 7b0a ld a,(OFST+7,sp)
858 0171 c75268 ld 21096,a
859 ; 226 }
862 0174 5b05 addw sp,#5
863 0176 81 ret
967 ; 240 void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode,
967 ; 241 TIM1_OutputState_TypeDef TIM1_OutputState,
967 ; 242 TIM1_OutputNState_TypeDef TIM1_OutputNState,
967 ; 243 u16 TIM1_Pulse,
967 ; 244 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
967 ; 245 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
967 ; 246 TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
967 ; 247 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
967 ; 248 {
968 switch .text
969 0177 _TIM1_OC3Init:
971 0177 89 pushw x
972 0178 5203 subw sp,#3
973 00000003 OFST: set 3
976 ; 251 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
978 ; 252 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
980 ; 253 assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
982 ; 254 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
984 ; 255 assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
986 ; 256 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
988 ; 257 assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
990 ; 260 TIM1->CCER2 &= (u8)(~( TIM1_CCER2_CC3E | TIM1_CCER2_CC3NE | TIM1_CCER2_CC3P | TIM1_CCER2_CC3NP));
992 017a c6525d ld a,21085
993 017d a4f0 and a,#240
994 017f c7525d ld 21085,a
995 ; 262 TIM1->CCER2 |= (u8)((TIM1_OutputState & TIM1_CCER2_CC3E ) | (TIM1_OutputNState & TIM1_CCER2_CC3NE ) | (TIM1_OCPolarity & TIM1_CCER2_CC3P ) | (TIM1_OCNPolarity & TIM1_CCER2_CC3NP ));
997 0182 7b0c ld a,(OFST+9,sp)
998 0184 a408 and a,#8
999 0186 6b03 ld (OFST+0,sp),a
1000 0188 7b0b ld a,(OFST+8,sp)
1001 018a a402 and a,#2
1002 018c 6b02 ld (OFST-1,sp),a
1003 018e 7b08 ld a,(OFST+5,sp)
1004 0190 a404 and a,#4
1005 0192 6b01 ld (OFST-2,sp),a
1006 0194 9f ld a,xl
1007 0195 a401 and a,#1
1008 0197 1a01 or a,(OFST-2,sp)
1009 0199 1a02 or a,(OFST-1,sp)
1010 019b 1a03 or a,(OFST+0,sp)
1011 019d ca525d or a,21085
1012 01a0 c7525d ld 21085,a
1013 ; 267 TIM1->CCMR3 = (u8)((TIM1->CCMR3 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode);
1015 01a3 c6525a ld a,21082
1016 01a6 a48f and a,#143
1017 01a8 1a04 or a,(OFST+1,sp)
1018 01aa c7525a ld 21082,a
1019 ; 270 TIM1->OISR &= (u8)(~(TIM1_OISR_OIS3 | TIM1_OISR_OIS3N));
1021 01ad c6526f ld a,21103
1022 01b0 a4cf and a,#207
1023 01b2 c7526f ld 21103,a
1024 ; 272 TIM1->OISR |= (u8)((TIM1_OISR_OIS3 & TIM1_OCIdleState) | (TIM1_OISR_OIS3N & TIM1_OCNIdleState));
1026 01b5 7b0e ld a,(OFST+11,sp)
1027 01b7 a420 and a,#32
1028 01b9 6b03 ld (OFST+0,sp),a
1029 01bb 7b0d ld a,(OFST+10,sp)
1030 01bd a410 and a,#16
1031 01bf 1a03 or a,(OFST+0,sp)
1032 01c1 ca526f or a,21103
1033 01c4 c7526f ld 21103,a
1034 ; 275 TIM1->CCR3H = (u8)(TIM1_Pulse >> 8);
1036 01c7 7b09 ld a,(OFST+6,sp)
1037 01c9 c75269 ld 21097,a
1038 ; 276 TIM1->CCR3L = (u8)(TIM1_Pulse);
1040 01cc 7b0a ld a,(OFST+7,sp)
1041 01ce c7526a ld 21098,a
1042 ; 278 }
1045 01d1 5b05 addw sp,#5
1046 01d3 81 ret
1120 ; 289 void TIM1_OC4Init(TIM1_OCMode_TypeDef TIM1_OCMode,
1120 ; 290 TIM1_OutputState_TypeDef TIM1_OutputState,
1120 ; 291 u16 TIM1_Pulse,
1120 ; 292 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
1120 ; 293 TIM1_OCIdleState_TypeDef TIM1_OCIdleState)
1120 ; 294 {
1121 switch .text
1122 01d4 _TIM1_OC4Init:
1124 01d4 89 pushw x
1125 01d5 88 push a
1126 00000001 OFST: set 1
1129 ; 297 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
1131 ; 298 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
1133 ; 299 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
1135 ; 300 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
1137 ; 305 TIM1->CCER2 &= (u8)(~(TIM1_CCER2_CC4E | TIM1_CCER2_CC4P));
1139 01d6 c6525d ld a,21085
1140 01d9 a4cf and a,#207
1141 01db c7525d ld 21085,a
1142 ; 307 TIM1->CCER2 |= (u8)((TIM1_OutputState & TIM1_CCER2_CC4E ) | (TIM1_OCPolarity & TIM1_CCER2_CC4P ));
1144 01de 7b08 ld a,(OFST+7,sp)
1145 01e0 a420 and a,#32
1146 01e2 6b01 ld (OFST+0,sp),a
1147 01e4 9f ld a,xl
1148 01e5 a410 and a,#16
1149 01e7 1a01 or a,(OFST+0,sp)
1150 01e9 ca525d or a,21085
1151 01ec c7525d ld 21085,a
1152 ; 310 TIM1->CCMR4 = (u8)((TIM1->CCMR4 & (u8)(~TIM1_CCMR_OCM)) | (TIM1_OCMode));
1154 01ef c6525b ld a,21083
1155 01f2 a48f and a,#143
1156 01f4 1a02 or a,(OFST+1,sp)
1157 01f6 c7525b ld 21083,a
1158 ; 313 if (TIM1_OCIdleState != TIM1_OCIDLESTATE_RESET)
1160 01f9 0d09 tnz (OFST+8,sp)
1161 01fb 270a jreq L534
1162 ; 315 TIM1->OISR |= (u8)(~TIM1_CCER2_CC4P);
1164 01fd c6526f ld a,21103
1165 0200 aadf or a,#223
1166 0202 c7526f ld 21103,a
1168 0205 2004 jra L734
1169 0207 L534:
1170 ; 319 TIM1->OISR &= (u8)(~TIM1_OISR_OIS4);
1172 0207 721d526f bres 21103,#6
1173 020b L734:
1174 ; 323 TIM1->CCR4H = (u8)(TIM1_Pulse >> 8);
1176 020b 7b06 ld a,(OFST+5,sp)
1177 020d c7526b ld 21099,a
1178 ; 324 TIM1->CCR4L = (u8)(TIM1_Pulse);
1180 0210 7b07 ld a,(OFST+6,sp)
1181 0212 c7526c ld 21100,a
1182 ; 326 }
1185 0215 5b03 addw sp,#3
1186 0217 81 ret
1391 ; 339 void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState,
1391 ; 340 TIM1_LockLevel_TypeDef TIM1_LockLevel,
1391 ; 341 u8 TIM1_DeadTime,
1391 ; 342 TIM1_BreakState_TypeDef TIM1_Break,
1391 ; 343 TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity,
1391 ; 344 TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
1391 ; 345 {
1392 switch .text
1393 0218 _TIM1_BDTRConfig:
1395 0218 89 pushw x
1396 00000000 OFST: set 0
1399 ; 349 assert_param(IS_TIM1_OSSI_STATE_OK(TIM1_OSSIState));
1401 ; 350 assert_param(IS_TIM1_LOCK_LEVEL_OK(TIM1_LockLevel));
1403 ; 351 assert_param(IS_TIM1_BREAK_STATE_OK(TIM1_Break));
1405 ; 352 assert_param(IS_TIM1_BREAK_POLARITY_OK(TIM1_BreakPolarity));
1407 ; 353 assert_param(IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(TIM1_AutomaticOutput));
1409 ; 356 TIM1->DTR = (u8)(TIM1_DeadTime);
1411 0219 7b05 ld a,(OFST+5,sp)
1412 021b c7526e ld 21102,a
1413 ; 360 TIM1->BKR = (u8)((u8)TIM1_OSSIState | \
1413 ; 361 (u8)TIM1_LockLevel | \
1413 ; 362 (u8)TIM1_Break | \
1413 ; 363 (u8)TIM1_BreakPolarity | \
1413 ; 364 (u8)TIM1_AutomaticOutput);
1415 021e 9f ld a,xl
1416 021f 1a01 or a,(OFST+1,sp)
1417 0221 1a06 or a,(OFST+6,sp)
1418 0223 1a07 or a,(OFST+7,sp)
1419 0225 1a08 or a,(OFST+8,sp)
1420 0227 c7526d ld 21101,a
1421 ; 366 }
1424 022a 85 popw x
1425 022b 81 ret
1627 ; 378 void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel,
1627 ; 379 TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
1627 ; 380 TIM1_ICSelection_TypeDef TIM1_ICSelection,
1627 ; 381 TIM1_ICPSC_TypeDef TIM1_ICPrescaler,
1627 ; 382 u8 TIM1_ICFilter)
1627 ; 383 {
1628 switch .text
1629 022c _TIM1_ICInit:
1631 022c 89 pushw x
1632 00000000 OFST: set 0
1635 ; 386 assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));
1637 ; 387 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
1639 ; 388 assert_param(IS_TIM1_IC_SELECTION_OK(TIM1_ICSelection));
1641 ; 389 assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_ICPrescaler));
1643 ; 390 assert_param(IS_TIM1_IC_FILTER_OK(TIM1_ICFilter));
1645 ; 392 if (TIM1_Channel == TIM1_CHANNEL_1)
1647 022d 9e ld a,xh
1648 022e 4d tnz a
1649 022f 2614 jrne L766
1650 ; 395 TI1_Config((u8)TIM1_ICPolarity,
1650 ; 396 (u8)TIM1_ICSelection,
1650 ; 397 (u8)TIM1_ICFilter);
1652 0231 7b07 ld a,(OFST+7,sp)
1653 0233 88 push a
1654 0234 7b06 ld a,(OFST+6,sp)
1655 0236 97 ld xl,a
1656 0237 7b03 ld a,(OFST+3,sp)
1657 0239 95 ld xh,a
1658 023a cd0815 call L3_TI1_Config
1660 023d 84 pop a
1661 ; 399 TIM1_SetIC1Prescaler(TIM1_ICPrescaler);
1663 023e 7b06 ld a,(OFST+6,sp)
1664 0240 cd06b1 call _TIM1_SetIC1Prescaler
1667 0243 2046 jra L176
1668 0245 L766:
1669 ; 401 else if (TIM1_Channel == TIM1_CHANNEL_2)
1671 0245 7b01 ld a,(OFST+1,sp)
1672 0247 a101 cp a,#1
1673 0249 2614 jrne L376
1674 ; 404 TI2_Config((u8)TIM1_ICPolarity,
1674 ; 405 (u8)TIM1_ICSelection,
1674 ; 406 (u8)TIM1_ICFilter);
1676 024b 7b07 ld a,(OFST+7,sp)
1677 024d 88 push a
1678 024e 7b06 ld a,(OFST+6,sp)
1679 0250 97 ld xl,a
1680 0251 7b03 ld a,(OFST+3,sp)
1681 0253 95 ld xh,a
1682 0254 cd0845 call L5_TI2_Config
1684 0257 84 pop a
1685 ; 408 TIM1_SetIC2Prescaler(TIM1_ICPrescaler);
1687 0258 7b06 ld a,(OFST+6,sp)
1688 025a cd06be call _TIM1_SetIC2Prescaler
1691 025d 202c jra L176
1692 025f L376:
1693 ; 410 else if (TIM1_Channel == TIM1_CHANNEL_3)
1695 025f 7b01 ld a,(OFST+1,sp)
1696 0261 a102 cp a,#2
1697 0263 2614 jrne L776
1698 ; 413 TI3_Config((u8)TIM1_ICPolarity,
1698 ; 414 (u8)TIM1_ICSelection,
1698 ; 415 (u8)TIM1_ICFilter);
1700 0265 7b07 ld a,(OFST+7,sp)
1701 0267 88 push a
1702 0268 7b06 ld a,(OFST+6,sp)
1703 026a 97 ld xl,a
1704 026b 7b03 ld a,(OFST+3,sp)
1705 026d 95 ld xh,a
1706 026e cd0875 call L7_TI3_Config
1708 0271 84 pop a
1709 ; 417 TIM1_SetIC3Prescaler(TIM1_ICPrescaler);
1711 0272 7b06 ld a,(OFST+6,sp)
1712 0274 cd06cb call _TIM1_SetIC3Prescaler
1715 0277 2012 jra L176
1716 0279 L776:
1717 ; 422 TI4_Config((u8)TIM1_ICPolarity,
1717 ; 423 (u8)TIM1_ICSelection,
1717 ; 424 (u8)TIM1_ICFilter);
1719 0279 7b07 ld a,(OFST+7,sp)
1720 027b 88 push a
1721 027c 7b06 ld a,(OFST+6,sp)
1722 027e 97 ld xl,a
1723 027f 7b03 ld a,(OFST+3,sp)
1724 0281 95 ld xh,a
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