📄 stm8s_tim1.ls
字号:
1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.9.2 - 29 Jun 2010
3 ; Generator V4.3.5 - 02 Jul 2010
43 ; 50 void TIM1_DeInit(void)
43 ; 51 {
45 switch .text
46 0000 _TIM1_DeInit:
50 ; 52 TIM1->CR1 = TIM1_CR1_RESET_VALUE;
52 0000 725f5250 clr 21072
53 ; 53 TIM1->CR2 = TIM1_CR2_RESET_VALUE;
55 0004 725f5251 clr 21073
56 ; 54 TIM1->SMCR = TIM1_SMCR_RESET_VALUE;
58 0008 725f5252 clr 21074
59 ; 55 TIM1->ETR = TIM1_ETR_RESET_VALUE;
61 000c 725f5253 clr 21075
62 ; 56 TIM1->IER = TIM1_IER_RESET_VALUE;
64 0010 725f5254 clr 21076
65 ; 57 TIM1->SR2 = TIM1_SR2_RESET_VALUE;
67 0014 725f5256 clr 21078
68 ; 59 TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;
70 0018 725f525c clr 21084
71 ; 60 TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;
73 001c 725f525d clr 21085
74 ; 62 TIM1->CCMR1 = 0x01;
76 0020 35015258 mov 21080,#1
77 ; 63 TIM1->CCMR2 = 0x01;
79 0024 35015259 mov 21081,#1
80 ; 64 TIM1->CCMR3 = 0x01;
82 0028 3501525a mov 21082,#1
83 ; 65 TIM1->CCMR4 = 0x01;
85 002c 3501525b mov 21083,#1
86 ; 67 TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;
88 0030 725f525c clr 21084
89 ; 68 TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;
91 0034 725f525d clr 21085
92 ; 69 TIM1->CCMR1 = TIM1_CCMR1_RESET_VALUE;
94 0038 725f5258 clr 21080
95 ; 70 TIM1->CCMR2 = TIM1_CCMR2_RESET_VALUE;
97 003c 725f5259 clr 21081
98 ; 71 TIM1->CCMR3 = TIM1_CCMR3_RESET_VALUE;
100 0040 725f525a clr 21082
101 ; 72 TIM1->CCMR4 = TIM1_CCMR4_RESET_VALUE;
103 0044 725f525b clr 21083
104 ; 73 TIM1->CNTRH = TIM1_CNTRH_RESET_VALUE;
106 0048 725f525e clr 21086
107 ; 74 TIM1->CNTRL = TIM1_CNTRL_RESET_VALUE;
109 004c 725f525f clr 21087
110 ; 75 TIM1->PSCRH = TIM1_PSCRH_RESET_VALUE;
112 0050 725f5260 clr 21088
113 ; 76 TIM1->PSCRL = TIM1_PSCRL_RESET_VALUE;
115 0054 725f5261 clr 21089
116 ; 77 TIM1->ARRH = TIM1_ARRH_RESET_VALUE;
118 0058 35ff5262 mov 21090,#255
119 ; 78 TIM1->ARRL = TIM1_ARRL_RESET_VALUE;
121 005c 35ff5263 mov 21091,#255
122 ; 79 TIM1->CCR1H = TIM1_CCR1H_RESET_VALUE;
124 0060 725f5265 clr 21093
125 ; 80 TIM1->CCR1L = TIM1_CCR1L_RESET_VALUE;
127 0064 725f5266 clr 21094
128 ; 81 TIM1->CCR2H = TIM1_CCR2H_RESET_VALUE;
130 0068 725f5267 clr 21095
131 ; 82 TIM1->CCR2L = TIM1_CCR2L_RESET_VALUE;
133 006c 725f5268 clr 21096
134 ; 83 TIM1->CCR3H = TIM1_CCR3H_RESET_VALUE;
136 0070 725f5269 clr 21097
137 ; 84 TIM1->CCR3L = TIM1_CCR3L_RESET_VALUE;
139 0074 725f526a clr 21098
140 ; 85 TIM1->CCR4H = TIM1_CCR4H_RESET_VALUE;
142 0078 725f526b clr 21099
143 ; 86 TIM1->CCR4L = TIM1_CCR4L_RESET_VALUE;
145 007c 725f526c clr 21100
146 ; 87 TIM1->OISR = TIM1_OISR_RESET_VALUE;
148 0080 725f526f clr 21103
149 ; 88 TIM1->EGR = 0x01; /* TIM1_EGR_UG */
151 0084 35015257 mov 21079,#1
152 ; 89 TIM1->DTR = TIM1_DTR_RESET_VALUE;
154 0088 725f526e clr 21102
155 ; 90 TIM1->BKR = TIM1_BKR_RESET_VALUE;
157 008c 725f526d clr 21101
158 ; 91 TIM1->RCR = TIM1_RCR_RESET_VALUE;
160 0090 725f5264 clr 21092
161 ; 92 TIM1->SR1 = TIM1_SR1_RESET_VALUE;
163 0094 725f5255 clr 21077
164 ; 93 }
167 0098 81 ret
276 ; 103 void TIM1_TimeBaseInit(u16 TIM1_Prescaler,
276 ; 104 TIM1_CounterMode_TypeDef TIM1_CounterMode,
276 ; 105 u16 TIM1_Period,
276 ; 106 u8 TIM1_RepetitionCounter)
276 ; 107 {
277 switch .text
278 0099 _TIM1_TimeBaseInit:
280 0099 89 pushw x
281 00000000 OFST: set 0
284 ; 110 assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));
286 ; 113 TIM1->ARRH = (u8)(TIM1_Period >> 8);
288 009a 7b06 ld a,(OFST+6,sp)
289 009c c75262 ld 21090,a
290 ; 114 TIM1->ARRL = (u8)(TIM1_Period);
292 009f 7b07 ld a,(OFST+7,sp)
293 00a1 c75263 ld 21091,a
294 ; 117 TIM1->PSCRH = (u8)(TIM1_Prescaler >> 8);
296 00a4 9e ld a,xh
297 00a5 c75260 ld 21088,a
298 ; 118 TIM1->PSCRL = (u8)(TIM1_Prescaler);
300 00a8 9f ld a,xl
301 00a9 c75261 ld 21089,a
302 ; 121 TIM1->CR1 = (u8)(((TIM1->CR1) & (u8)(~(TIM1_CR1_CMS | TIM1_CR1_DIR))) | (u8)(TIM1_CounterMode));
304 00ac c65250 ld a,21072
305 00af a48f and a,#143
306 00b1 1a05 or a,(OFST+5,sp)
307 00b3 c75250 ld 21072,a
308 ; 124 TIM1->RCR = TIM1_RepetitionCounter;
310 00b6 7b08 ld a,(OFST+8,sp)
311 00b8 c75264 ld 21092,a
312 ; 126 }
315 00bb 85 popw x
316 00bc 81 ret
601 ; 140 void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode,
601 ; 141 TIM1_OutputState_TypeDef TIM1_OutputState,
601 ; 142 TIM1_OutputNState_TypeDef TIM1_OutputNState,
601 ; 143 u16 TIM1_Pulse,
601 ; 144 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
601 ; 145 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
601 ; 146 TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
601 ; 147 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
601 ; 148 {
602 switch .text
603 00bd _TIM1_OC1Init:
605 00bd 89 pushw x
606 00be 5203 subw sp,#3
607 00000003 OFST: set 3
610 ; 150 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
612 ; 151 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
614 ; 152 assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
616 ; 153 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
618 ; 154 assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
620 ; 155 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
622 ; 156 assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
624 ; 159 TIM1->CCER1 &= (u8)(~( TIM1_CCER1_CC1E | TIM1_CCER1_CC1NE | TIM1_CCER1_CC1P | TIM1_CCER1_CC1NP));
626 00c0 c6525c ld a,21084
627 00c3 a4f0 and a,#240
628 00c5 c7525c ld 21084,a
629 ; 161 TIM1->CCER1 |= (u8)((TIM1_OutputState & TIM1_CCER1_CC1E ) | (TIM1_OutputNState & TIM1_CCER1_CC1NE ) | (TIM1_OCPolarity & TIM1_CCER1_CC1P ) | (TIM1_OCNPolarity & TIM1_CCER1_CC1NP ));
631 00c8 7b0c ld a,(OFST+9,sp)
632 00ca a408 and a,#8
633 00cc 6b03 ld (OFST+0,sp),a
634 00ce 7b0b ld a,(OFST+8,sp)
635 00d0 a402 and a,#2
636 00d2 6b02 ld (OFST-1,sp),a
637 00d4 7b08 ld a,(OFST+5,sp)
638 00d6 a404 and a,#4
639 00d8 6b01 ld (OFST-2,sp),a
640 00da 9f ld a,xl
641 00db a401 and a,#1
642 00dd 1a01 or a,(OFST-2,sp)
643 00df 1a02 or a,(OFST-1,sp)
644 00e1 1a03 or a,(OFST+0,sp)
645 00e3 ca525c or a,21084
646 00e6 c7525c ld 21084,a
647 ; 164 TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode);
649 00e9 c65258 ld a,21080
650 00ec a48f and a,#143
651 00ee 1a04 or a,(OFST+1,sp)
652 00f0 c75258 ld 21080,a
653 ; 167 TIM1->OISR &= (u8)(~(TIM1_OISR_OIS1 | TIM1_OISR_OIS1N));
655 00f3 c6526f ld a,21103
656 00f6 a4fc and a,#252
657 00f8 c7526f ld 21103,a
658 ; 169 TIM1->OISR |= (u8)(( TIM1_OCIdleState & TIM1_OISR_OIS1 ) | ( TIM1_OCNIdleState & TIM1_OISR_OIS1N ));
660 00fb 7b0e ld a,(OFST+11,sp)
661 00fd a402 and a,#2
662 00ff 6b03 ld (OFST+0,sp),a
663 0101 7b0d ld a,(OFST+10,sp)
664 0103 a401 and a,#1
665 0105 1a03 or a,(OFST+0,sp)
666 0107 ca526f or a,21103
667 010a c7526f ld 21103,a
668 ; 172 TIM1->CCR1H = (u8)(TIM1_Pulse >> 8);
670 010d 7b09 ld a,(OFST+6,sp)
671 010f c75265 ld 21093,a
672 ; 173 TIM1->CCR1L = (u8)(TIM1_Pulse);
674 0112 7b0a ld a,(OFST+7,sp)
675 0114 c75266 ld 21094,a
676 ; 174 }
679 0117 5b05 addw sp,#5
680 0119 81 ret
784 ; 188 void TIM1_OC2Init(TIM1_OCMode_TypeDef TIM1_OCMode,
784 ; 189 TIM1_OutputState_TypeDef TIM1_OutputState,
784 ; 190 TIM1_OutputNState_TypeDef TIM1_OutputNState,
784 ; 191 u16 TIM1_Pulse,
784 ; 192 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
784 ; 193 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
784 ; 194 TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
784 ; 195 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
784 ; 196 {
785 switch .text
786 011a _TIM1_OC2Init:
788 011a 89 pushw x
789 011b 5203 subw sp,#3
790 00000003 OFST: set 3
793 ; 200 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
795 ; 201 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
797 ; 202 assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
799 ; 203 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
801 ; 204 assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
803 ; 205 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
805 ; 206 assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
807 ; 209 TIM1->CCER1 &= (u8)(~( TIM1_CCER1_CC2E | TIM1_CCER1_CC2NE | TIM1_CCER1_CC2P | TIM1_CCER1_CC2NP));
809 011d c6525c ld a,21084
810 0120 a40f and a,#15
811 0122 c7525c ld 21084,a
812 ; 211 TIM1->CCER1 |= (u8)((TIM1_OutputState & TIM1_CCER1_CC2E ) | (TIM1_OutputNState & TIM1_CCER1_CC2NE ) | (TIM1_OCPolarity & TIM1_CCER1_CC2P ) | (TIM1_OCNPolarity & TIM1_CCER1_CC2NP ));
814 0125 7b0c ld a,(OFST+9,sp)
815 0127 a480 and a,#128
816 0129 6b03 ld (OFST+0,sp),a
817 012b 7b0b ld a,(OFST+8,sp)
818 012d a420 and a,#32
819 012f 6b02 ld (OFST-1,sp),a
820 0131 7b08 ld a,(OFST+5,sp)
821 0133 a440 and a,#64
822 0135 6b01 ld (OFST-2,sp),a
823 0137 9f ld a,xl
824 0138 a410 and a,#16
825 013a 1a01 or a,(OFST-2,sp)
826 013c 1a02 or a,(OFST-1,sp)
827 013e 1a03 or a,(OFST+0,sp)
828 0140 ca525c or a,21084
829 0143 c7525c ld 21084,a
830 ; 215 TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode);
832 0146 c65259 ld a,21081
833 0149 a48f and a,#143
834 014b 1a04 or a,(OFST+1,sp)
835 014d c75259 ld 21081,a
836 ; 218 TIM1->OISR &= (u8)(~(TIM1_OISR_OIS2 | TIM1_OISR_OIS2N));
838 0150 c6526f ld a,21103
839 0153 a4f3 and a,#243
840 0155 c7526f ld 21103,a
841 ; 220 TIM1->OISR |= (u8)((TIM1_OISR_OIS2 & TIM1_OCIdleState) | (TIM1_OISR_OIS2N & TIM1_OCNIdleState));
843 0158 7b0e ld a,(OFST+11,sp)
844 015a a408 and a,#8
845 015c 6b03 ld (OFST+0,sp),a
846 015e 7b0d ld a,(OFST+10,sp)
847 0160 a404 and a,#4
848 0162 1a03 or a,(OFST+0,sp)
849 0164 ca526f or a,21103
850 0167 c7526f ld 21103,a
851 ; 223 TIM1->CCR2H = (u8)(TIM1_Pulse >> 8);
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