📄 stm8s_tim2.ls
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3639 03fa 9f ld a,xl
3640 03fb 6b02 ld (OFST-2,sp),a
3641 ; 1091 tim2_flag_h = (u8)(TIM2_FLAG >> 8);
3643 03fd 9e ld a,xh
3644 03fe 6b03 ld (OFST-1,sp),a
3645 ; 1093 if (((TIM2->SR1 & tim2_flag_l) | (TIM2->SR2 & tim2_flag_h)) != (u8)RESET )
3647 0400 c65303 ld a,21251
3648 0403 1403 and a,(OFST-1,sp)
3649 0405 6b01 ld (OFST-3,sp),a
3650 0407 c65302 ld a,21250
3651 040a 1402 and a,(OFST-2,sp)
3652 040c 1a01 or a,(OFST-3,sp)
3653 040e 2706 jreq L7271
3654 ; 1095 bitstatus = SET;
3656 0410 a601 ld a,#1
3657 0412 6b04 ld (OFST+0,sp),a
3659 0414 2002 jra L1371
3660 0416 L7271:
3661 ; 1099 bitstatus = RESET;
3663 0416 0f04 clr (OFST+0,sp)
3664 0418 L1371:
3665 ; 1101 return (FlagStatus)bitstatus;
3667 0418 7b04 ld a,(OFST+0,sp)
3670 041a 5b04 addw sp,#4
3671 041c 81 ret
3706 ; 1118 void TIM2_ClearFlag(TIM2_FLAG_TypeDef TIM2_FLAG)
3706 ; 1119 {
3707 switch .text
3708 041d _TIM2_ClearFlag:
3710 041d 89 pushw x
3711 00000000 OFST: set 0
3714 ; 1121 assert_param(IS_TIM2_CLEAR_FLAG_OK(TIM2_FLAG));
3716 ; 1124 TIM2->SR1 = (u8)(~((u8)(TIM2_FLAG)));
3718 041e 9f ld a,xl
3719 041f 43 cpl a
3720 0420 c75302 ld 21250,a
3721 ; 1125 TIM2->SR2 = (u8)(~((u8)(TIM2_FLAG >> 8)));
3723 0423 7b01 ld a,(OFST+1,sp)
3724 0425 43 cpl a
3725 0426 c75303 ld 21251,a
3726 ; 1126 }
3729 0429 85 popw x
3730 042a 81 ret
3794 ; 1140 ITStatus TIM2_GetITStatus(TIM2_IT_TypeDef TIM2_IT)
3794 ; 1141 {
3795 switch .text
3796 042b _TIM2_GetITStatus:
3798 042b 88 push a
3799 042c 5203 subw sp,#3
3800 00000003 OFST: set 3
3803 ; 1142 volatile ITStatus bitstatus = RESET;
3805 042e 0f03 clr (OFST+0,sp)
3806 ; 1143 vu8 TIM2_itStatus = 0, TIM2_itEnable = 0;
3808 0430 0f01 clr (OFST-2,sp)
3811 0432 0f02 clr (OFST-1,sp)
3812 ; 1146 assert_param(IS_TIM2_GET_IT_OK(TIM2_IT));
3814 ; 1148 TIM2_itStatus = (u8)(TIM2->SR1 & TIM2_IT);
3816 0434 c45302 and a,21250
3817 0437 6b01 ld (OFST-2,sp),a
3818 ; 1150 TIM2_itEnable = (u8)(TIM2->IER & TIM2_IT);
3820 0439 c65301 ld a,21249
3821 043c 1404 and a,(OFST+1,sp)
3822 043e 6b02 ld (OFST-1,sp),a
3823 ; 1152 if ((TIM2_itStatus != (u8)RESET ) && (TIM2_itEnable != (u8)RESET ))
3825 0440 0d01 tnz (OFST-2,sp)
3826 0442 270a jreq L3002
3828 0444 0d02 tnz (OFST-1,sp)
3829 0446 2706 jreq L3002
3830 ; 1154 bitstatus = SET;
3832 0448 a601 ld a,#1
3833 044a 6b03 ld (OFST+0,sp),a
3835 044c 2002 jra L5002
3836 044e L3002:
3837 ; 1158 bitstatus = RESET;
3839 044e 0f03 clr (OFST+0,sp)
3840 0450 L5002:
3841 ; 1160 return (ITStatus)(bitstatus);
3843 0450 7b03 ld a,(OFST+0,sp)
3846 0452 5b04 addw sp,#4
3847 0454 81 ret
3883 ; 1174 void TIM2_ClearITPendingBit(TIM2_IT_TypeDef TIM2_IT)
3883 ; 1175 {
3884 switch .text
3885 0455 _TIM2_ClearITPendingBit:
3889 ; 1177 assert_param(IS_TIM2_IT_OK(TIM2_IT));
3891 ; 1180 TIM2->SR1 = (u8)(~TIM2_IT);
3893 0455 43 cpl a
3894 0456 c75302 ld 21250,a
3895 ; 1181 }
3898 0459 81 ret
3950 ; 1200 static void TI1_Config(u8 TIM2_ICPolarity,
3950 ; 1201 u8 TIM2_ICSelection,
3950 ; 1202 u8 TIM2_ICFilter)
3950 ; 1203 {
3951 switch .text
3952 045a L3_TI1_Config:
3954 045a 89 pushw x
3955 045b 88 push a
3956 00000001 OFST: set 1
3959 ; 1205 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC1E);
3961 045c 72115308 bres 21256,#0
3962 ; 1208 TIM2->CCMR1 = (u8)((TIM2->CCMR1 & (u8)(~( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF ))) | (u8)(( (TIM2_ICSelection)) | ((u8)( TIM2_ICFilter << 4))));
3964 0460 7b06 ld a,(OFST+5,sp)
3965 0462 97 ld xl,a
3966 0463 a610 ld a,#16
3967 0465 42 mul x,a
3968 0466 9f ld a,xl
3969 0467 1a03 or a,(OFST+2,sp)
3970 0469 6b01 ld (OFST+0,sp),a
3971 046b c65305 ld a,21253
3972 046e a40c and a,#12
3973 0470 1a01 or a,(OFST+0,sp)
3974 0472 c75305 ld 21253,a
3975 ; 1211 if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)
3977 0475 0d02 tnz (OFST+1,sp)
3978 0477 2706 jreq L3502
3979 ; 1213 TIM2->CCER1 |= TIM2_CCER1_CC1P;
3981 0479 72125308 bset 21256,#1
3983 047d 2004 jra L5502
3984 047f L3502:
3985 ; 1217 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC1P);
3987 047f 72135308 bres 21256,#1
3988 0483 L5502:
3989 ; 1220 TIM2->CCER1 |= TIM2_CCER1_CC1E;
3991 0483 72105308 bset 21256,#0
3992 ; 1221 }
3995 0487 5b03 addw sp,#3
3996 0489 81 ret
4048 ; 1240 static void TI2_Config(u8 TIM2_ICPolarity,
4048 ; 1241 u8 TIM2_ICSelection,
4048 ; 1242 u8 TIM2_ICFilter)
4048 ; 1243 {
4049 switch .text
4050 048a L5_TI2_Config:
4052 048a 89 pushw x
4053 048b 88 push a
4054 00000001 OFST: set 1
4057 ; 1245 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC2E);
4059 048c 72195308 bres 21256,#4
4060 ; 1248 TIM2->CCMR2 = (u8)((TIM2->CCMR2 & (u8)(~( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF ))) | (u8)(( (TIM2_ICSelection)) | ((u8)( TIM2_ICFilter << 4))));
4062 0490 7b06 ld a,(OFST+5,sp)
4063 0492 97 ld xl,a
4064 0493 a610 ld a,#16
4065 0495 42 mul x,a
4066 0496 9f ld a,xl
4067 0497 1a03 or a,(OFST+2,sp)
4068 0499 6b01 ld (OFST+0,sp),a
4069 049b c65306 ld a,21254
4070 049e a40c and a,#12
4071 04a0 1a01 or a,(OFST+0,sp)
4072 04a2 c75306 ld 21254,a
4073 ; 1252 if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)
4075 04a5 0d02 tnz (OFST+1,sp)
4076 04a7 2706 jreq L5012
4077 ; 1254 TIM2->CCER1 |= TIM2_CCER1_CC2P;
4079 04a9 721a5308 bset 21256,#5
4081 04ad 2004 jra L7012
4082 04af L5012:
4083 ; 1258 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC2P);
4085 04af 721b5308 bres 21256,#5
4086 04b3 L7012:
4087 ; 1262 TIM2->CCER1 |= TIM2_CCER1_CC2E;
4089 04b3 72185308 bset 21256,#4
4090 ; 1264 }
4093 04b7 5b03 addw sp,#3
4094 04b9 81 ret
4146 ; 1280 static void TI3_Config(u8 TIM2_ICPolarity, u8 TIM2_ICSelection,
4146 ; 1281 u8 TIM2_ICFilter)
4146 ; 1282 {
4147 switch .text
4148 04ba L7_TI3_Config:
4150 04ba 89 pushw x
4151 04bb 88 push a
4152 00000001 OFST: set 1
4155 ; 1284 TIM2->CCER2 &= (u8)(~TIM2_CCER2_CC3E);
4157 04bc 72115309 bres 21257,#0
4158 ; 1287 TIM2->CCMR3 = (u8)((TIM2->CCMR3 & (u8)(~( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF ))) | (u8)(( (TIM2_ICSelection)) | ((u8)( TIM2_ICFilter << 4))));
4160 04c0 7b06 ld a,(OFST+5,sp)
4161 04c2 97 ld xl,a
4162 04c3 a610 ld a,#16
4163 04c5 42 mul x,a
4164 04c6 9f ld a,xl
4165 04c7 1a03 or a,(OFST+2,sp)
4166 04c9 6b01 ld (OFST+0,sp),a
4167 04cb c65307 ld a,21255
4168 04ce a40c and a,#12
4169 04d0 1a01 or a,(OFST+0,sp)
4170 04d2 c75307 ld 21255,a
4171 ; 1291 if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)
4173 04d5 0d02 tnz (OFST+1,sp)
4174 04d7 2706 jreq L7312
4175 ; 1293 TIM2->CCER2 |= TIM2_CCER2_CC3P;
4177 04d9 72125309 bset 21257,#1
4179 04dd 2004 jra L1412
4180 04df L7312:
4181 ; 1297 TIM2->CCER2 &= (u8)(~TIM2_CCER2_CC3P);
4183 04df 72135309 bres 21257,#1
4184 04e3 L1412:
4185 ; 1300 TIM2->CCER2 |= TIM2_CCER2_CC3E;
4187 04e3 72105309 bset 21257,#0
4188 ; 1301 }
4191 04e7 5b03 addw sp,#3
4192 04e9 81 ret
4205 xdef _TIM2_ClearITPendingBit
4206 xdef _TIM2_GetITStatus
4207 xdef _TIM2_ClearFlag
4208 xdef _TIM2_GetFlagStatus
4209 xdef _TIM2_GetPrescaler
4210 xdef _TIM2_GetCounter
4211 xdef _TIM2_GetCapture3
4212 xdef _TIM2_GetCapture2
4213 xdef _TIM2_GetCapture1
4214 xdef _TIM2_SetIC3Prescaler
4215 xdef _TIM2_SetIC2Prescaler
4216 xdef _TIM2_SetIC1Prescaler
4217 xdef _TIM2_SetCompare3
4218 xdef _TIM2_SetCompare2
4219 xdef _TIM2_SetCompare1
4220 xdef _TIM2_SetAutoreload
4221 xdef _TIM2_SetCounter
4222 xdef _TIM2_SelectOCxM
4223 xdef _TIM2_CCxCmd
4224 xdef _TIM2_OC3PolarityConfig
4225 xdef _TIM2_OC2PolarityConfig
4226 xdef _TIM2_OC1PolarityConfig
4227 xdef _TIM2_GenerateEvent
4228 xdef _TIM2_OC3PreloadConfig
4229 xdef _TIM2_OC2PreloadConfig
4230 xdef _TIM2_OC1PreloadConfig
4231 xdef _TIM2_ARRPreloadConfig
4232 xdef _TIM2_ForcedOC3Config
4233 xdef _TIM2_ForcedOC2Config
4234 xdef _TIM2_ForcedOC1Config
4235 xdef _TIM2_PrescalerConfig
4236 xdef _TIM2_SelectOnePulseMode
4237 xdef _TIM2_UpdateRequestConfig
4238 xdef _TIM2_UpdateDisableConfig
4239 xdef _TIM2_ITConfig
4240 xdef _TIM2_Cmd
4241 xdef _TIM2_PWMIConfig
4242 xdef _TIM2_ICInit
4243 xdef _TIM2_OC3Init
4244 xdef _TIM2_OC2Init
4245 xdef _TIM2_OC1Init
4246 xdef _TIM2_TimeBaseInit
4247 xdef _TIM2_DeInit
4266 end
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