📄 stm8s_tim2.ls
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1879 ; 529 TIM2->CCMR2 = (u8)((TIM2->CCMR2 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_ForcedAction);
1881 021e c65306 ld a,21254
1882 0221 a48f and a,#143
1883 0223 1a01 or a,(OFST+1,sp)
1884 0225 c75306 ld 21254,a
1885 ; 530 }
1888 0228 84 pop a
1889 0229 81 ret
1925 ; 541 void TIM2_ForcedOC3Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
1925 ; 542 {
1926 switch .text
1927 022a _TIM2_ForcedOC3Config:
1929 022a 88 push a
1930 00000000 OFST: set 0
1933 ; 544 assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));
1935 ; 547 TIM2->CCMR3 = (u8)((TIM2->CCMR3 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_ForcedAction);
1937 022b c65307 ld a,21255
1938 022e a48f and a,#143
1939 0230 1a01 or a,(OFST+1,sp)
1940 0232 c75307 ld 21255,a
1941 ; 548 }
1944 0235 84 pop a
1945 0236 81 ret
1981 ; 557 void TIM2_ARRPreloadConfig(FunctionalState NewState)
1981 ; 558 {
1982 switch .text
1983 0237 _TIM2_ARRPreloadConfig:
1987 ; 560 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1989 ; 563 if (NewState != DISABLE)
1991 0237 4d tnz a
1992 0238 2706 jreq L7201
1993 ; 565 TIM2->CR1 |= (u8)TIM2_CR1_ARPE;
1995 023a 721e5300 bset 21248,#7
1997 023e 2004 jra L1301
1998 0240 L7201:
1999 ; 569 TIM2->CR1 &= (u8)(~TIM2_CR1_ARPE);
2001 0240 721f5300 bres 21248,#7
2002 0244 L1301:
2003 ; 571 }
2006 0244 81 ret
2042 ; 580 void TIM2_OC1PreloadConfig(FunctionalState NewState)
2042 ; 581 {
2043 switch .text
2044 0245 _TIM2_OC1PreloadConfig:
2048 ; 583 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2050 ; 586 if (NewState != DISABLE)
2052 0245 4d tnz a
2053 0246 2706 jreq L1501
2054 ; 588 TIM2->CCMR1 |= (u8)TIM2_CCMR_OCxPE;
2056 0248 72165305 bset 21253,#3
2058 024c 2004 jra L3501
2059 024e L1501:
2060 ; 592 TIM2->CCMR1 &= (u8)(~TIM2_CCMR_OCxPE);
2062 024e 72175305 bres 21253,#3
2063 0252 L3501:
2064 ; 594 }
2067 0252 81 ret
2103 ; 603 void TIM2_OC2PreloadConfig(FunctionalState NewState)
2103 ; 604 {
2104 switch .text
2105 0253 _TIM2_OC2PreloadConfig:
2109 ; 606 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2111 ; 609 if (NewState != DISABLE)
2113 0253 4d tnz a
2114 0254 2706 jreq L3701
2115 ; 611 TIM2->CCMR2 |= (u8)TIM2_CCMR_OCxPE;
2117 0256 72165306 bset 21254,#3
2119 025a 2004 jra L5701
2120 025c L3701:
2121 ; 615 TIM2->CCMR2 &= (u8)(~TIM2_CCMR_OCxPE);
2123 025c 72175306 bres 21254,#3
2124 0260 L5701:
2125 ; 617 }
2128 0260 81 ret
2164 ; 626 void TIM2_OC3PreloadConfig(FunctionalState NewState)
2164 ; 627 {
2165 switch .text
2166 0261 _TIM2_OC3PreloadConfig:
2170 ; 629 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2172 ; 632 if (NewState != DISABLE)
2174 0261 4d tnz a
2175 0262 2706 jreq L5111
2176 ; 634 TIM2->CCMR3 |= (u8)TIM2_CCMR_OCxPE;
2178 0264 72165307 bset 21255,#3
2180 0268 2004 jra L7111
2181 026a L5111:
2182 ; 638 TIM2->CCMR3 &= (u8)(~TIM2_CCMR_OCxPE);
2184 026a 72175307 bres 21255,#3
2185 026e L7111:
2186 ; 640 }
2189 026e 81 ret
2262 ; 653 void TIM2_GenerateEvent(TIM2_EventSource_TypeDef TIM2_EventSource)
2262 ; 654 {
2263 switch .text
2264 026f _TIM2_GenerateEvent:
2268 ; 656 assert_param(IS_TIM2_EVENT_SOURCE_OK(TIM2_EventSource));
2270 ; 659 TIM2->EGR = (u8)TIM2_EventSource;
2272 026f c75304 ld 21252,a
2273 ; 660 }
2276 0272 81 ret
2312 ; 671 void TIM2_OC1PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
2312 ; 672 {
2313 switch .text
2314 0273 _TIM2_OC1PolarityConfig:
2318 ; 674 assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
2320 ; 677 if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)
2322 0273 4d tnz a
2323 0274 2706 jreq L1711
2324 ; 679 TIM2->CCER1 |= (u8)TIM2_CCER1_CC1P;
2326 0276 72125308 bset 21256,#1
2328 027a 2004 jra L3711
2329 027c L1711:
2330 ; 683 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC1P);
2332 027c 72135308 bres 21256,#1
2333 0280 L3711:
2334 ; 685 }
2337 0280 81 ret
2373 ; 696 void TIM2_OC2PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
2373 ; 697 {
2374 switch .text
2375 0281 _TIM2_OC2PolarityConfig:
2379 ; 699 assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
2381 ; 702 if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)
2383 0281 4d tnz a
2384 0282 2706 jreq L3121
2385 ; 704 TIM2->CCER1 |= TIM2_CCER1_CC2P;
2387 0284 721a5308 bset 21256,#5
2389 0288 2004 jra L5121
2390 028a L3121:
2391 ; 708 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC2P);
2393 028a 721b5308 bres 21256,#5
2394 028e L5121:
2395 ; 710 }
2398 028e 81 ret
2434 ; 721 void TIM2_OC3PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
2434 ; 722 {
2435 switch .text
2436 028f _TIM2_OC3PolarityConfig:
2440 ; 724 assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
2442 ; 727 if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)
2444 028f 4d tnz a
2445 0290 2706 jreq L5321
2446 ; 729 TIM2->CCER2 |= (u8)TIM2_CCER2_CC3P;
2448 0292 72125309 bset 21257,#1
2450 0296 2004 jra L7321
2451 0298 L5321:
2452 ; 733 TIM2->CCER2 &= (u8)(~TIM2_CCER2_CC3P);
2454 0298 72135309 bres 21257,#1
2455 029c L7321:
2456 ; 735 }
2459 029c 81 ret
2504 ; 749 void TIM2_CCxCmd(TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState)
2504 ; 750 {
2505 switch .text
2506 029d _TIM2_CCxCmd:
2508 029d 89 pushw x
2509 00000000 OFST: set 0
2512 ; 752 assert_param(IS_TIM2_CHANNEL_OK(TIM2_Channel));
2514 ; 753 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2516 ; 755 if (TIM2_Channel == TIM2_CHANNEL_1)
2518 029e 9e ld a,xh
2519 029f 4d tnz a
2520 02a0 2610 jrne L3621
2521 ; 758 if (NewState != DISABLE)
2523 02a2 9f ld a,xl
2524 02a3 4d tnz a
2525 02a4 2706 jreq L5621
2526 ; 760 TIM2->CCER1 |= (u8)TIM2_CCER1_CC1E;
2528 02a6 72105308 bset 21256,#0
2530 02aa 202a jra L1721
2531 02ac L5621:
2532 ; 764 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC1E);
2534 02ac 72115308 bres 21256,#0
2535 02b0 2024 jra L1721
2536 02b2 L3621:
2537 ; 768 else if (TIM2_Channel == TIM2_CHANNEL_2)
2539 02b2 7b01 ld a,(OFST+1,sp)
2540 02b4 a101 cp a,#1
2541 02b6 2610 jrne L3721
2542 ; 771 if (NewState != DISABLE)
2544 02b8 0d02 tnz (OFST+2,sp)
2545 02ba 2706 jreq L5721
2546 ; 773 TIM2->CCER1 |= (u8)TIM2_CCER1_CC2E;
2548 02bc 72185308 bset 21256,#4
2550 02c0 2014 jra L1721
2551 02c2 L5721:
2552 ; 777 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC2E);
2554 02c2 72195308 bres 21256,#4
2555 02c6 200e jra L1721
2556 02c8 L3721:
2557 ; 783 if (NewState != DISABLE)
2559 02c8 0d02 tnz (OFST+2,sp)
2560 02ca 2706 jreq L3031
2561 ; 785 TIM2->CCER2 |= (u8)TIM2_CCER2_CC3E;
2563 02cc 72105309 bset 21257,#0
2565 02d0 2004 jra L1721
2566 02d2 L3031:
2567 ; 789 TIM2->CCER2 &= (u8)(~TIM2_CCER2_CC3E);
2569 02d2 72115309 bres 21257,#0
2570 02d6 L1721:
2571 ; 792 }
2574 02d6 85 popw x
2575 02d7 81 ret
2620 ; 814 void TIM2_SelectOCxM(TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode)
2620 ; 815 {
2621 switch .text
2622 02d8 _TIM2_SelectOCxM:
2624 02d8 89 pushw x
2625 00000000 OFST: set 0
2628 ; 817 assert_param(IS_TIM2_CHANNEL_OK(TIM2_Channel));
2630 ; 818 assert_param(IS_TIM2_OCM_OK(TIM2_OCMode));
2632 ; 820 if (TIM2_Channel == TIM2_CHANNEL_1)
2634 02d9 9e ld a,xh
2635 02da 4d tnz a
2636 02db 2610 jrne L1331
2637 ; 823 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC1E);
2639 02dd 72115308 bres 21256,#0
2640 ; 826 TIM2->CCMR1 = (u8)((TIM2->CCMR1 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_OCMode);
2642 02e1 c65305 ld a,21253
2643 02e4 a48f and a,#143
2644 02e6 1a02 or a,(OFST+2,sp)
2645 02e8 c75305 ld 21253,a
2647 02eb 2024 jra L3331
2648 02ed L1331:
2649 ; 828 else if (TIM2_Channel == TIM2_CHANNEL_2)
2651 02ed 7b01 ld a,(OFST+1,sp)
2652 02ef a101 cp a,#1
2653 02f1 2610 jrne L5331
2654 ; 831 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC2E);
2656 02f3 72195308 bres 21256,#4
2657 ; 834 TIM2->CCMR2 = (u8)((TIM2->CCMR2 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_OCMode);
2659 02f7 c65306 ld a,21254
2660 02fa a48f and a,#143
2661 02fc 1a02 or a,(OFST+2,sp)
2662 02fe c75306 ld 21254,a
2664 0301 200e jra L3331
2665 0303 L5331:
2666 ; 839 TIM2->CCER2 &= (u8)(~TIM2_CCER2_CC3E);
2668 0303 72115309 bres 21257,#0
2669 ; 842 TIM2->CCMR3 = (u8)((TIM2->CCMR3 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_OCMode);
2671 0307 c65307 ld a,21255
2672 030a a48f and a,#143
2673 030c 1a02 or a,(OFST+2,sp)
2674 030e c75307 ld 21255,a
2675 0311 L3331:
2676 ; 844 }
2679 0311 85 popw x
2680 0312 81 ret
2714 ; 853 void TIM2_SetCounter(u16 Counter)
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