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📄 stm8s_adc1.ls

📁 STM8s
💻 LS
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1299  0169 85            	popw	x
1300  016a 81            	ret
1346                     ; 341 void ADC1_ExternalTriggerConfig(ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState NewState)
1346                     ; 342 {
1347                     	switch	.text
1348  016b               _ADC1_ExternalTriggerConfig:
1350  016b 89            	pushw	x
1351       00000000      OFST:	set	0
1354                     ; 345     assert_param(IS_ADC1_EXTTRIG_OK(ADC1_ExtTrigger));
1356                     ; 346     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1358                     ; 349     ADC1->CR2 &= (u8)(~ADC1_CR2_EXTSEL);
1360  016c c65402        	ld	a,21506
1361  016f a4cf          	and	a,#207
1362  0171 c75402        	ld	21506,a
1363                     ; 351     if (NewState != DISABLE)
1365  0174 9f            	ld	a,xl
1366  0175 4d            	tnz	a
1367  0176 2706          	jreq	L555
1368                     ; 354         ADC1->CR2 |= (u8)(ADC1_CR2_EXTTRIG);
1370  0178 721c5402      	bset	21506,#6
1372  017c 2004          	jra	L755
1373  017e               L555:
1374                     ; 359         ADC1->CR2 &= (u8)(~ADC1_CR2_EXTTRIG);
1376  017e 721d5402      	bres	21506,#6
1377  0182               L755:
1378                     ; 363     ADC1->CR2 |= (u8)(ADC1_ExtTrigger);
1380  0182 c65402        	ld	a,21506
1381  0185 1a01          	or	a,(OFST+1,sp)
1382  0187 c75402        	ld	21506,a
1383                     ; 365 }
1386  018a 85            	popw	x
1387  018b 81            	ret
1411                     ; 378 void ADC1_StartConversion(void)
1411                     ; 379 {
1412                     	switch	.text
1413  018c               _ADC1_StartConversion:
1417                     ; 380     ADC1->CR1 |= ADC1_CR1_ADON;
1419  018c 72105401      	bset	21505,#0
1420                     ; 381 }
1423  0190 81            	ret
1467                     ; 391 u16 ADC1_GetConversionValue(void)
1467                     ; 392 {
1468                     	switch	.text
1469  0191               _ADC1_GetConversionValue:
1471  0191 5205          	subw	sp,#5
1472       00000005      OFST:	set	5
1475                     ; 394     u16 temph = 0;
1477                     ; 395     u8 templ = 0;
1479                     ; 397     if (ADC1->CR2 & ADC1_CR2_ALIGN) /* Right alignment */
1481  0193 c65402        	ld	a,21506
1482  0196 a508          	bcp	a,#8
1483  0198 2715          	jreq	L316
1484                     ; 400         templ = ADC1->DRL;
1486  019a c65405        	ld	a,21509
1487  019d 6b03          	ld	(OFST-2,sp),a
1488                     ; 402         temph = ADC1->DRH;
1490  019f c65404        	ld	a,21508
1491  01a2 5f            	clrw	x
1492  01a3 97            	ld	xl,a
1493  01a4 1f04          	ldw	(OFST-1,sp),x
1494                     ; 404         temph = (u16)(templ | (u16)(temph << (u8)8));
1496  01a6 1e04          	ldw	x,(OFST-1,sp)
1497  01a8 7b03          	ld	a,(OFST-2,sp)
1498  01aa 02            	rlwa	x,a
1499  01ab 1f04          	ldw	(OFST-1,sp),x
1501  01ad 2021          	jra	L516
1502  01af               L316:
1503                     ; 409         temph = ADC1->DRH;
1505  01af c65404        	ld	a,21508
1506  01b2 5f            	clrw	x
1507  01b3 97            	ld	xl,a
1508  01b4 1f04          	ldw	(OFST-1,sp),x
1509                     ; 411         templ = ADC1->DRL;
1511  01b6 c65405        	ld	a,21509
1512  01b9 6b03          	ld	(OFST-2,sp),a
1513                     ; 413         temph = (u16)((u16)(templ << (u8)6) | (u16)(temph << (u8)8));
1515  01bb 1e04          	ldw	x,(OFST-1,sp)
1516  01bd 4f            	clr	a
1517  01be 02            	rlwa	x,a
1518  01bf 1f01          	ldw	(OFST-4,sp),x
1519  01c1 7b03          	ld	a,(OFST-2,sp)
1520  01c3 97            	ld	xl,a
1521  01c4 a640          	ld	a,#64
1522  01c6 42            	mul	x,a
1523  01c7 01            	rrwa	x,a
1524  01c8 1a02          	or	a,(OFST-3,sp)
1525  01ca 01            	rrwa	x,a
1526  01cb 1a01          	or	a,(OFST-4,sp)
1527  01cd 01            	rrwa	x,a
1528  01ce 1f04          	ldw	(OFST-1,sp),x
1529  01d0               L516:
1530                     ; 416     return ((u16)temph);
1532  01d0 1e04          	ldw	x,(OFST-1,sp)
1535  01d2 5b05          	addw	sp,#5
1536  01d4 81            	ret
1582                     ; 428 void ADC1_AWDChannelConfig(ADC1_Channel_TypeDef Channel, FunctionalState NewState)
1582                     ; 429 {
1583                     	switch	.text
1584  01d5               _ADC1_AWDChannelConfig:
1586  01d5 89            	pushw	x
1587       00000000      OFST:	set	0
1590                     ; 431     assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1592                     ; 432     assert_param(IS_ADC1_CHANNEL_OK(Channel));
1594                     ; 434     if (Channel < (u8)8)
1596  01d6 9e            	ld	a,xh
1597  01d7 a108          	cp	a,#8
1598  01d9 242e          	jruge	L146
1599                     ; 436         if (NewState != DISABLE)
1601  01db 9f            	ld	a,xl
1602  01dc 4d            	tnz	a
1603  01dd 2714          	jreq	L346
1604                     ; 438             ADC1->AWCRL |= (u8)((u8)1 << Channel);
1606  01df 9e            	ld	a,xh
1607  01e0 5f            	clrw	x
1608  01e1 97            	ld	xl,a
1609  01e2 a601          	ld	a,#1
1610  01e4 5d            	tnzw	x
1611  01e5 2704          	jreq	L65
1612  01e7               L06:
1613  01e7 48            	sll	a
1614  01e8 5a            	decw	x
1615  01e9 26fc          	jrne	L06
1616  01eb               L65:
1617  01eb ca540f        	or	a,21519
1618  01ee c7540f        	ld	21519,a
1620  01f1 2047          	jra	L746
1621  01f3               L346:
1622                     ; 442             ADC1->AWCRL &= (u8)(~((u8)1 << Channel));
1624  01f3 7b01          	ld	a,(OFST+1,sp)
1625  01f5 5f            	clrw	x
1626  01f6 97            	ld	xl,a
1627  01f7 a601          	ld	a,#1
1628  01f9 5d            	tnzw	x
1629  01fa 2704          	jreq	L26
1630  01fc               L46:
1631  01fc 48            	sll	a
1632  01fd 5a            	decw	x
1633  01fe 26fc          	jrne	L46
1634  0200               L26:
1635  0200 43            	cpl	a
1636  0201 c4540f        	and	a,21519
1637  0204 c7540f        	ld	21519,a
1638  0207 2031          	jra	L746
1639  0209               L146:
1640                     ; 447         if (NewState != DISABLE)
1642  0209 0d02          	tnz	(OFST+2,sp)
1643  020b 2717          	jreq	L156
1644                     ; 449             ADC1->AWCRH |= (u8)((u8)1 << (Channel - (u8)8));
1646  020d 7b01          	ld	a,(OFST+1,sp)
1647  020f a008          	sub	a,#8
1648  0211 5f            	clrw	x
1649  0212 97            	ld	xl,a
1650  0213 a601          	ld	a,#1
1651  0215 5d            	tnzw	x
1652  0216 2704          	jreq	L66
1653  0218               L07:
1654  0218 48            	sll	a
1655  0219 5a            	decw	x
1656  021a 26fc          	jrne	L07
1657  021c               L66:
1658  021c ca540e        	or	a,21518
1659  021f c7540e        	ld	21518,a
1661  0222 2016          	jra	L746
1662  0224               L156:
1663                     ; 453             ADC1->AWCRH &= (u8)(~((u8)1 << (Channel - (u8)8)));
1665  0224 7b01          	ld	a,(OFST+1,sp)
1666  0226 a008          	sub	a,#8
1667  0228 5f            	clrw	x
1668  0229 97            	ld	xl,a
1669  022a a601          	ld	a,#1
1670  022c 5d            	tnzw	x
1671  022d 2704          	jreq	L27
1672  022f               L47:
1673  022f 48            	sll	a
1674  0230 5a            	decw	x
1675  0231 26fc          	jrne	L47
1676  0233               L27:
1677  0233 43            	cpl	a
1678  0234 c4540e        	and	a,21518
1679  0237 c7540e        	ld	21518,a
1680  023a               L746:
1681                     ; 456 }
1684  023a 85            	popw	x
1685  023b 81            	ret
1720                     ; 464 void ADC1_SetHighThreshold(u16 Threshold)
1720                     ; 465 {
1721                     	switch	.text
1722  023c               _ADC1_SetHighThreshold:
1726                     ; 466     ADC1->HTRH = (u8)(Threshold >> (u8)8);
1728  023c 9e            	ld	a,xh
1729  023d c75408        	ld	21512,a
1730                     ; 467     ADC1->HTRL = (u8)Threshold;
1732  0240 9f            	ld	a,xl
1733  0241 c75409        	ld	21513,a
1734                     ; 468 }
1737  0244 81            	ret
1772                     ; 476 void ADC1_SetLowThreshold(u16 Threshold)
1772                     ; 477 {
1773                     	switch	.text
1774  0245               _ADC1_SetLowThreshold:
1778                     ; 478     ADC1->LTRL = (u8)Threshold;
1780  0245 9f            	ld	a,xl
1781  0246 c7540b        	ld	21515,a
1782                     ; 479     ADC1->LTRH = (u8)(Threshold >> (u8)8);
1784  0249 9e            	ld	a,xh
1785  024a c7540a        	ld	21514,a
1786                     ; 480 }
1789  024d 81            	ret
1842                     ; 489 u16 ADC1_GetBufferValue(u8 Buffer)
1842                     ; 490 {
1843                     	switch	.text
1844  024e               _ADC1_GetBufferValue:
1846  024e 88            	push	a
1847  024f 5205          	subw	sp,#5
1848       00000005      OFST:	set	5
1851                     ; 492     u16 temph = 0;
1853                     ; 493     u8 templ = 0;
1855                     ; 496     assert_param(IS_ADC1_BUFFER_OK(Buffer));
1857                     ; 498     if (ADC1->CR2 & ADC1_CR2_ALIGN) /* Right alignment */
1859  0251 c65402        	ld	a,21506
1860  0254 a508          	bcp	a,#8
1861  0256 271f          	jreq	L737
1862                     ; 501         templ = *(u8*)(ADC1_BaseAddress + (Buffer << 1) + 1);
1864  0258 7b06          	ld	a,(OFST+1,sp)
1865  025a 5f            	clrw	x
1866  025b 97            	ld	xl,a
1867  025c 58            	sllw	x
1868  025d d653e1        	ld	a,(21473,x)
1869  0260 6b03          	ld	(OFST-2,sp),a
1870                     ; 503         temph = *(u8*)(ADC1_BaseAddress + (Buffer << 1));
1872  0262 7b06          	ld	a,(OFST+1,sp)
1873  0264 5f            	clrw	x
1874  0265 97            	ld	xl,a
1875  0266 58            	sllw	x
1876  0267 d653e0        	ld	a,(21472,x)
1877  026a 5f            	clrw	x
1878  026b 97            	ld	xl,a
1879  026c 1f04          	ldw	(OFST-1,sp),x
1880                     ; 505         temph = (u16)(templ | (u16)(temph << (u8)8));
1882  026e 1e04          	ldw	x,(OFST-1,sp)
1883  0270 7b03          	ld	a,(OFST-2,sp)
1884  0272 02            	rlwa	x,a
1885  0273 1f04          	ldw	(OFST-1,sp),x
1887  0275 202b          	jra	L147
1888  0277               L737:
1889                     ; 510         temph = *(u8*)(ADC1_BaseAddress + (Buffer << 1));
1891  0277 7b06          	ld	a,(OFST+1,sp)
1892  0279 5f            	clrw	x
1893  027a 97            	ld	xl,a
1894  027b 58            	sllw	x
1895  027c d653e0        	ld	a,(21472,x)
1896  027f 5f            	clrw	x
1897  0280 97            	ld	xl,a
1898  0281 1f04          	ldw	(OFST-1,sp),x
1899                     ; 512         templ = *(u8*)(ADC1_BaseAddress + (Buffer << 1) + 1);
1901  0283 7b06          	ld	a,(OFST+1,sp)
1902  0285 5f            	clrw	x
1903  0286 97            	ld	xl,a
1904  0287 58            	sllw	x
1905  0288 d653e1        	ld	a,(21473,x)
1906  028b 6b03          	ld	(OFST-2,sp),a
1907                     ; 514         temph = (u16)((u16)(templ << (u8)6) | (u16)(temph << (u8)8));
1909  028d 1e04          	ldw	x,(OFST-1,sp)
1910  028f 4f            	clr	a
1911  0290 02            	rlwa	x,a
1912  0291 1f01          	ldw	(OFST-4,sp),x
1913  0293 7b03          	ld	a,(OFST-2,sp)
1914  0295 97            	ld	xl,a
1915  0296 a640          	ld	a,#64
1916  0298 42            	mul	x,a
1917  0299 01            	rrwa	x,a
1918  029a 1a02          	or	a,(OFST-3,sp)
1919  029c 01            	rrwa	x,a
1920  029d 1a01          	or	a,(OFST-4,sp)
1921  029f 01            	rrwa	x,a
1922  02a0 1f04          	ldw	(OFST-1,sp),x
1923  02a2               L147:
1924                     ; 517     return ((u16)temph);
1926  02a2 1e04          	ldw	x,(OFST-1,sp)
1929  02a4 5b06          	addw	sp,#6
1930  02a6 81            	ret
1996                     ; 527 FlagStatus ADC1_GetAWDChannelStatus(ADC1_Channel_TypeDef Channel)
1996                     ; 528 {
1997                     	switch	.text
1998  02a7               _ADC1_GetAWDChannelStatus:
2000  02a7 88            	push	a
2001  02a8 88            	push	a
2002       00000001      OFST:	set	1
2005                     ; 529     u8 status = 0;
2007                     ; 532     assert_param(IS_ADC1_CHANNEL_OK(Channel));
2009                     ; 534     if (Channel < (u8)8)
2011  02a9 a108          	cp	a,#8
2012  02ab 2412          	jruge	L577
2013                     ; 536         status = (u8)(ADC1->AWSRL & ((u8)1 << Channel));
2015  02ad 5f            	clrw	x
2016  02ae 97            	ld	xl,a
2017  02af a601          	ld	a,#1
2018  02b1 5d            	tnzw	x
2019  02b2 2704          	jreq	L601
2020  02b4               L011:
2021  02b4 48            	sll	a
2022  02b5 5a            	decw	x
2023  02b6 26fc          	jrne	L011
2024  02b8               L601:
2025  02b8 c4540d        	and	a,21517
2026  02bb 6b01          	ld	(OFST+0,sp),a
2028  02bd 2014          	jra	L777
2029  02bf               L577:
2030                     ; 540         status = (u8)(ADC1->AWSRH & ((u8)1 << (Channel - (u8)8)));
2032  02bf 7b02          	ld	a,(OFST+1,sp)
2033  02c1 a008          	sub	a,#8
2034  02c3 5f            	clrw	x
2035  02c4 97            	ld	xl,a
2036  02c5 a601          	ld	a,#1
2037  02c7 5d            	tnzw	x
2038  02c8 2704          	jreq	L211
2039  02ca               L411:
2040  02ca 48            	sll	a

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