📄 stm8s_uart2.ls
字号:
2119 ; 616 UART2->PSCR = UART2_Prescaler;
2121 0307 c7524b ld 21067,a
2122 ; 617 }
2125 030a 81 ret
2282 ; 628 FlagStatus UART2_GetFlagStatus(UART2_Flag_TypeDef UART2_FLAG)
2282 ; 629 {
2283 switch .text
2284 030b _UART2_GetFlagStatus:
2286 030b 89 pushw x
2287 030c 88 push a
2288 00000001 OFST: set 1
2291 ; 630 FlagStatus status = RESET;
2293 ; 633 assert_param(IS_UART2_FLAG_OK(UART2_FLAG));
2295 ; 636 if (UART2_FLAG == UART2_FLAG_LBDF)
2297 030d a30210 cpw x,#528
2298 0310 2610 jrne L3611
2299 ; 638 if ((UART2->CR4 & (u8)UART2_FLAG) != (u8)0x00)
2301 0312 9f ld a,xl
2302 0313 c45247 and a,21063
2303 0316 2706 jreq L5611
2304 ; 641 status = SET;
2306 0318 a601 ld a,#1
2307 031a 6b01 ld (OFST+0,sp),a
2309 031c 2039 jra L1711
2310 031e L5611:
2311 ; 646 status = RESET;
2313 031e 0f01 clr (OFST+0,sp)
2314 0320 2035 jra L1711
2315 0322 L3611:
2316 ; 649 else if (UART2_FLAG == UART2_FLAG_SBK)
2318 0322 1e02 ldw x,(OFST+1,sp)
2319 0324 a30101 cpw x,#257
2320 0327 2611 jrne L3711
2321 ; 651 if ((UART2->CR2 & (u8)UART2_FLAG) != (u8)0x00)
2323 0329 c65245 ld a,21061
2324 032c 1503 bcp a,(OFST+2,sp)
2325 032e 2706 jreq L5711
2326 ; 654 status = SET;
2328 0330 a601 ld a,#1
2329 0332 6b01 ld (OFST+0,sp),a
2331 0334 2021 jra L1711
2332 0336 L5711:
2333 ; 659 status = RESET;
2335 0336 0f01 clr (OFST+0,sp)
2336 0338 201d jra L1711
2337 033a L3711:
2338 ; 662 else if ((UART2_FLAG == UART2_FLAG_LHDF) || (UART2_FLAG == UART2_FLAG_LSF))
2340 033a 1e02 ldw x,(OFST+1,sp)
2341 033c a30302 cpw x,#770
2342 033f 2707 jreq L5021
2344 0341 1e02 ldw x,(OFST+1,sp)
2345 0343 a30301 cpw x,#769
2346 0346 2614 jrne L3021
2347 0348 L5021:
2348 ; 664 if ((UART2->CR6 & (u8)UART2_FLAG) != (u8)0x00)
2350 0348 c65249 ld a,21065
2351 034b 1503 bcp a,(OFST+2,sp)
2352 034d 2706 jreq L7021
2353 ; 667 status = SET;
2355 034f a601 ld a,#1
2356 0351 6b01 ld (OFST+0,sp),a
2358 0353 2002 jra L1711
2359 0355 L7021:
2360 ; 672 status = RESET;
2362 0355 0f01 clr (OFST+0,sp)
2363 0357 L1711:
2364 ; 690 return status;
2366 0357 7b01 ld a,(OFST+0,sp)
2369 0359 5b03 addw sp,#3
2370 035b 81 ret
2371 035c L3021:
2372 ; 677 if ((UART2->SR & (u8)UART2_FLAG) != (u8)0x00)
2374 035c c65240 ld a,21056
2375 035f 1503 bcp a,(OFST+2,sp)
2376 0361 2706 jreq L5121
2377 ; 680 status = SET;
2379 0363 a601 ld a,#1
2380 0365 6b01 ld (OFST+0,sp),a
2382 0367 20ee jra L1711
2383 0369 L5121:
2384 ; 685 status = RESET;
2386 0369 0f01 clr (OFST+0,sp)
2387 036b 20ea jra L1711
2422 ; 718 void UART2_ClearFlag(UART2_Flag_TypeDef UART2_FLAG)
2422 ; 719 {
2423 switch .text
2424 036d _UART2_ClearFlag:
2426 036d 89 pushw x
2427 00000000 OFST: set 0
2430 ; 720 assert_param(IS_UART2_CLEAR_FLAG_OK(UART2_FLAG));
2432 ; 723 if (UART2_FLAG == UART2_FLAG_RXNE)
2434 036e a30020 cpw x,#32
2435 0371 2606 jrne L7321
2436 ; 725 UART2->SR = (u8)~(UART2_SR_RXNE);
2438 0373 35df5240 mov 21056,#223
2440 0377 201e jra L1421
2441 0379 L7321:
2442 ; 728 else if (UART2_FLAG == UART2_FLAG_LBDF)
2444 0379 1e01 ldw x,(OFST+1,sp)
2445 037b a30210 cpw x,#528
2446 037e 2606 jrne L3421
2447 ; 730 UART2->CR4 &= (u8)(~UART2_CR4_LBDF);
2449 0380 72195247 bres 21063,#4
2451 0384 2011 jra L1421
2452 0386 L3421:
2453 ; 733 else if (UART2_FLAG == UART2_FLAG_LHDF)
2455 0386 1e01 ldw x,(OFST+1,sp)
2456 0388 a30302 cpw x,#770
2457 038b 2606 jrne L7421
2458 ; 735 UART2->CR6 &= (u8)(~UART2_CR6_LHDF);
2460 038d 72135249 bres 21065,#1
2462 0391 2004 jra L1421
2463 0393 L7421:
2464 ; 740 UART2->CR6 &= (u8)(~UART2_CR6_LSF);
2466 0393 72115249 bres 21065,#0
2467 0397 L1421:
2468 ; 743 }
2471 0397 85 popw x
2472 0398 81 ret
2554 ; 761 ITStatus UART2_GetITStatus(UART2_IT_TypeDef UART2_IT)
2554 ; 762 {
2555 switch .text
2556 0399 _UART2_GetITStatus:
2558 0399 89 pushw x
2559 039a 89 pushw x
2560 00000002 OFST: set 2
2563 ; 763 ITStatus pendingbitstatus = RESET;
2565 ; 764 u8 itpos = 0;
2567 ; 765 u8 itmask1 = 0;
2569 ; 766 u8 itmask2 = 0;
2571 ; 767 u8 enablestatus = 0;
2573 ; 770 assert_param(IS_UART2_GET_IT_OK(UART2_IT));
2575 ; 773 itpos = (u8)((u8)1 << (u8)((u8)UART2_IT & (u8)0x0F));
2577 039b 9f ld a,xl
2578 039c a40f and a,#15
2579 039e 5f clrw x
2580 039f 97 ld xl,a
2581 03a0 a601 ld a,#1
2582 03a2 5d tnzw x
2583 03a3 2704 jreq L27
2584 03a5 L47:
2585 03a5 48 sll a
2586 03a6 5a decw x
2587 03a7 26fc jrne L47
2588 03a9 L27:
2589 03a9 6b01 ld (OFST-1,sp),a
2590 ; 775 itmask1 = (u8)((u8)UART2_IT >> (u8)4);
2592 03ab 7b04 ld a,(OFST+2,sp)
2593 03ad 4e swap a
2594 03ae a40f and a,#15
2595 03b0 6b02 ld (OFST+0,sp),a
2596 ; 777 itmask2 = (u8)((u8)1 << itmask1);
2598 03b2 7b02 ld a,(OFST+0,sp)
2599 03b4 5f clrw x
2600 03b5 97 ld xl,a
2601 03b6 a601 ld a,#1
2602 03b8 5d tnzw x
2603 03b9 2704 jreq L67
2604 03bb L001:
2605 03bb 48 sll a
2606 03bc 5a decw x
2607 03bd 26fc jrne L001
2608 03bf L67:
2609 03bf 6b02 ld (OFST+0,sp),a
2610 ; 782 if (UART2_IT == UART2_IT_PE)
2612 03c1 1e03 ldw x,(OFST+1,sp)
2613 03c3 a30100 cpw x,#256
2614 03c6 261c jrne L5131
2615 ; 785 enablestatus = (u8)((u8)UART2->CR1 & itmask2);
2617 03c8 c65244 ld a,21060
2618 03cb 1402 and a,(OFST+0,sp)
2619 03cd 6b02 ld (OFST+0,sp),a
2620 ; 788 if (((UART2->SR & itpos) != (u8)0x00) && enablestatus)
2622 03cf c65240 ld a,21056
2623 03d2 1501 bcp a,(OFST-1,sp)
2624 03d4 270a jreq L7131
2626 03d6 0d02 tnz (OFST+0,sp)
2627 03d8 2706 jreq L7131
2628 ; 791 pendingbitstatus = SET;
2630 03da a601 ld a,#1
2631 03dc 6b02 ld (OFST+0,sp),a
2633 03de 2064 jra L3231
2634 03e0 L7131:
2635 ; 796 pendingbitstatus = RESET;
2637 03e0 0f02 clr (OFST+0,sp)
2638 03e2 2060 jra L3231
2639 03e4 L5131:
2640 ; 800 else if (UART2_IT == UART2_IT_LBDF)
2642 03e4 1e03 ldw x,(OFST+1,sp)
2643 03e6 a30346 cpw x,#838
2644 03e9 261c jrne L5231
2645 ; 803 enablestatus = (u8)((u8)UART2->CR4 & itmask2);
2647 03eb c65247 ld a,21063
2648 03ee 1402 and a,(OFST+0,sp)
2649 03f0 6b02 ld (OFST+0,sp),a
2650 ; 805 if (((UART2->CR4 & itpos) != (u8)0x00) && enablestatus)
2652 03f2 c65247 ld a,21063
2653 03f5 1501 bcp a,(OFST-1,sp)
2654 03f7 270a jreq L7231
2656 03f9 0d02 tnz (OFST+0,sp)
2657 03fb 2706 jreq L7231
2658 ; 808 pendingbitstatus = SET;
2660 03fd a601 ld a,#1
2661 03ff 6b02 ld (OFST+0,sp),a
2663 0401 2041 jra L3231
2664 0403 L7231:
2665 ; 813 pendingbitstatus = RESET;
2667 0403 0f02 clr (OFST+0,sp)
2668 0405 203d jra L3231
2669 0407 L5231:
2670 ; 816 else if (UART2_IT == UART2_IT_LHDF)
2672 0407 1e03 ldw x,(OFST+1,sp)
2673 0409 a30412 cpw x,#1042
2674 040c 261c jrne L5331
2675 ; 819 enablestatus = (u8)((u8)UART2->CR6 & itmask2);
2677 040e c65249 ld a,21065
2678 0411 1402 and a,(OFST+0,sp)
2679 0413 6b02 ld (OFST+0,sp),a
2680 ; 821 if (((UART2->CR6 & itpos) != (u8)0x00) && enablestatus)
2682 0415 c65249 ld a,21065
2683 0418 1501 bcp a,(OFST-1,sp)
2684 041a 270a jreq L7331
2686 041c 0d02 tnz (OFST+0,sp)
2687 041e 2706 jreq L7331
2688 ; 824 pendingbitstatus = SET;
2690 0420 a601 ld a,#1
2691 0422 6b02 ld (OFST+0,sp),a
2693 0424 201e jra L3231
2694 0426 L7331:
2695 ; 829 pendingbitstatus = RESET;
2697 0426 0f02 clr (OFST+0,sp)
2698 0428 201a jra L3231
2699 042a L5331:
2700 ; 835 enablestatus = (u8)((u8)UART2->CR2 & itmask2);
2702 042a c65245 ld a,21061
2703 042d 1402 and a,(OFST+0,sp)
2704 042f 6b02 ld (OFST+0,sp),a
2705 ; 837 if (((UART2->SR & itpos) != (u8)0x00) && enablestatus)
2707 0431 c65240 ld a,21056
2708 0434 1501 bcp a,(OFST-1,sp)
2709 0436 270a jreq L5431
2711 0438 0d02 tnz (OFST+0,sp)
2712 043a 2706 jreq L5431
2713 ; 840 pendingbitstatus = SET;
2715 043c a601 ld a,#1
2716 043e 6b02 ld (OFST+0,sp),a
2718 0440 2002 jra L3231
2719 0442 L5431:
2720 ; 845 pendingbitstatus = RESET;
2722 0442 0f02 clr (OFST+0,sp)
2723 0444 L3231:
2724 ; 849 return pendingbitstatus;
2726 0444 7b02 ld a,(OFST+0,sp)
2729 0446 5b04 addw sp,#4
2730 0448 81 ret
2766 ; 876 void UART2_ClearITPendingBit(UART2_IT_TypeDef UART2_IT)
2766 ; 877 {
2767 switch .text
2768 0449 _UART2_ClearITPendingBit:
2770 0449 89 pushw x
2771 00000000 OFST: set 0
2774 ; 878 assert_param(IS_UART2_CLEAR_IT_OK(UART2_IT));
2776 ; 881 if (UART2_IT == UART2_IT_RXNE)
2778 044a a30255 cpw x,#597
2779 044d 2606 jrne L7631
2780 ; 883 UART2->SR = (u8)~(UART2_SR_RXNE);
2782 044f 35df5240 mov 21056,#223
2784 0453 2011 jra L1731
2785 0455 L7631:
2786 ; 886 else if (UART2_IT == UART2_IT_LBDF)
2788 0455 1e01 ldw x,(OFST+1,sp)
2789 0457 a30346 cpw x,#838
2790 045a 2606 jrne L3731
2791 ; 888 UART2->CR4 &= (u8)~(UART2_CR4_LBDF);
2793 045c 72195247 bres 21063,#4
2795 0460 2004 jra L1731
2796 0462 L3731:
2797 ; 893 UART2->CR6 &= (u8)(~UART2_CR6_LHDF);
2799 0462 72135249 bres 21065,#1
2800 0466 L1731:
2801 ; 895 }
2804 0466 85 popw x
2805 0467 81 ret
2840 ; 898 void putChr(char a)
2840 ; 899 {
2841 switch .text
2842 0468 _putChr:
2846 ; 900 UART2_SendData8(a);
2848 0468 cd02c5 call _UART2_SendData8
2850 ; 901 }
2853 046b 81 ret
2888 ; 904 void putChrLine(char a)
2888 ; 905 {
2889 switch .text
2890 046c _putChrLine:
2894 ; 906 putChr(a);
2896 046c adfa call _putChr
2898 ; 907 putChr('\r');
2900 046e a60d ld a,#13
2901 0470 adf6 call _putChr
2903 ; 908 putChr('\n');
2905 0472 a60a ld a,#10
2906 0474 adf2 call _putChr
2908 ; 909 }
2911 0476 81 ret
2957 ; 913 void putStr(char* a)
2957 ; 914 {
2958 switch .text
2959 0477 _putStr:
2961 0477 89 pushw x
2962 0478 89 pushw x
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