📄 stm8s_uart2.ls
字号:
977 01df 43 cpl a
978 01e0 c45245 and a,21061
979 01e3 c75245 ld 21061,a
981 01e6 201a jra L553
982 01e8 L363:
983 ; 237 else if (uartreg == 0x03)
985 01e8 7b01 ld a,(OFST-1,sp)
986 01ea a103 cp a,#3
987 01ec 260b jrne L763
988 ; 239 UART2->CR4 &= (u8)(~itpos);
990 01ee 7b02 ld a,(OFST+0,sp)
991 01f0 43 cpl a
992 01f1 c45247 and a,21063
993 01f4 c75247 ld 21063,a
995 01f7 2009 jra L553
996 01f9 L763:
997 ; 243 UART2->CR6 &= (u8)(~itpos);
999 01f9 7b02 ld a,(OFST+0,sp)
1000 01fb 43 cpl a
1001 01fc c45249 and a,21065
1002 01ff c75249 ld 21065,a
1003 0202 L553:
1004 ; 246 }
1007 0202 5b04 addw sp,#4
1008 0204 81 ret
1065 ; 256 void UART2_IrDAConfig(UART2_IrDAMode_TypeDef UART2_IrDAMode)
1065 ; 257 {
1066 switch .text
1067 0205 _UART2_IrDAConfig:
1071 ; 258 assert_param(IS_UART2_IRDAMODE_OK(UART2_IrDAMode));
1073 ; 260 if (UART2_IrDAMode != UART2_IRDAMODE_NORMAL)
1075 0205 4d tnz a
1076 0206 2706 jreq L124
1077 ; 262 UART2->CR5 |= UART2_CR5_IRLP;
1079 0208 72145248 bset 21064,#2
1081 020c 2004 jra L324
1082 020e L124:
1083 ; 266 UART2->CR5 &= ((u8)~UART2_CR5_IRLP);
1085 020e 72155248 bres 21064,#2
1086 0212 L324:
1087 ; 268 }
1090 0212 81 ret
1125 ; 279 void UART2_IrDACmd(FunctionalState NewState)
1125 ; 280 {
1126 switch .text
1127 0213 _UART2_IrDACmd:
1131 ; 283 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1133 ; 285 if (NewState != DISABLE)
1135 0213 4d tnz a
1136 0214 2706 jreq L344
1137 ; 288 UART2->CR5 |= UART2_CR5_IREN;
1139 0216 72125248 bset 21064,#1
1141 021a 2004 jra L544
1142 021c L344:
1143 ; 293 UART2->CR5 &= ((u8)~UART2_CR5_IREN);
1145 021c 72135248 bres 21064,#1
1146 0220 L544:
1147 ; 295 }
1150 0220 81 ret
1209 ; 305 void UART2_LINBreakDetectionConfig(UART2_LINBreakDetectionLength_TypeDef UART2_LINBreakDetectionLength)
1209 ; 306 {
1210 switch .text
1211 0221 _UART2_LINBreakDetectionConfig:
1215 ; 307 assert_param(IS_UART2_LINBREAKDETECTIONLENGTH_OK(UART2_LINBreakDetectionLength));
1217 ; 309 if (UART2_LINBreakDetectionLength != UART2_LINBREAKDETECTIONLENGTH_10BITS)
1219 0221 4d tnz a
1220 0222 2706 jreq L574
1221 ; 311 UART2->CR4 |= UART2_CR4_LBDL;
1223 0224 721a5247 bset 21063,#5
1225 0228 2004 jra L774
1226 022a L574:
1227 ; 315 UART2->CR4 &= ((u8)~UART2_CR4_LBDL);
1229 022a 721b5247 bres 21063,#5
1230 022e L774:
1231 ; 317 }
1234 022e 81 ret
1355 ; 331 void UART2_LINConfig(UART2_LinMode_TypeDef UART2_Mode, UART2_LinAutosync_TypeDef UART2_Autosync, UART2_LinDivUp_TypeDef UART2_DivUp)
1355 ; 332 {
1356 switch .text
1357 022f _UART2_LINConfig:
1359 022f 89 pushw x
1360 00000000 OFST: set 0
1363 ; 333 assert_param(IS_UART2_SLAVE_OK(UART2_Mode));
1365 ; 335 assert_param(IS_UART2_AUTOSYNC_OK(UART2_Autosync));
1367 ; 337 assert_param(IS_UART2_DIVUP_OK(UART2_DivUp));
1369 ; 339 if (UART2_Mode != UART2_LIN_MODE_MASTER)
1371 0230 9e ld a,xh
1372 0231 4d tnz a
1373 0232 2706 jreq L755
1374 ; 341 UART2->CR6 |= UART2_CR6_LSLV;
1376 0234 721a5249 bset 21065,#5
1378 0238 2004 jra L165
1379 023a L755:
1380 ; 345 UART2->CR6 &= ((u8)~UART2_CR6_LSLV);
1382 023a 721b5249 bres 21065,#5
1383 023e L165:
1384 ; 348 if (UART2_Autosync != UART2_LIN_AUTOSYNC_DISABLE)
1386 023e 0d02 tnz (OFST+2,sp)
1387 0240 2706 jreq L365
1388 ; 350 UART2->CR6 |= UART2_CR6_LASE ;
1390 0242 72185249 bset 21065,#4
1392 0246 2004 jra L565
1393 0248 L365:
1394 ; 354 UART2->CR6 &= ((u8)~ UART2_CR6_LASE );
1396 0248 72195249 bres 21065,#4
1397 024c L565:
1398 ; 357 if (UART2_DivUp != UART2_LIN_DIVUP_LBRR1)
1400 024c 0d05 tnz (OFST+5,sp)
1401 024e 2706 jreq L765
1402 ; 359 UART2->CR6 |= UART2_CR6_LDUM;
1404 0250 721e5249 bset 21065,#7
1406 0254 2004 jra L175
1407 0256 L765:
1408 ; 363 UART2->CR6 &= ((u8)~ UART2_CR6_LDUM);
1410 0256 721f5249 bres 21065,#7
1411 025a L175:
1412 ; 366 }
1415 025a 85 popw x
1416 025b 81 ret
1451 ; 378 void UART2_LINCmd(FunctionalState NewState)
1451 ; 379 {
1452 switch .text
1453 025c _UART2_LINCmd:
1457 ; 380 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1459 ; 382 if (NewState != DISABLE)
1461 025c 4d tnz a
1462 025d 2706 jreq L116
1463 ; 385 UART2->CR3 |= UART2_CR3_LINEN;
1465 025f 721c5246 bset 21062,#6
1467 0263 2004 jra L316
1468 0265 L116:
1469 ; 390 UART2->CR3 &= ((u8)~UART2_CR3_LINEN);
1471 0265 721d5246 bres 21062,#6
1472 0269 L316:
1473 ; 392 }
1476 0269 81 ret
1511 ; 402 void UART2_SmartCardCmd(FunctionalState NewState)
1511 ; 403 {
1512 switch .text
1513 026a _UART2_SmartCardCmd:
1517 ; 404 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1519 ; 406 if (NewState != DISABLE)
1521 026a 4d tnz a
1522 026b 2706 jreq L336
1523 ; 409 UART2->CR5 |= UART2_CR5_SCEN;
1525 026d 721a5248 bset 21064,#5
1527 0271 2004 jra L536
1528 0273 L336:
1529 ; 414 UART2->CR5 &= ((u8)(~UART2_CR5_SCEN));
1531 0273 721b5248 bres 21064,#5
1532 0277 L536:
1533 ; 416 }
1536 0277 81 ret
1572 ; 427 void UART2_SmartCardNACKCmd(FunctionalState NewState)
1572 ; 428 {
1573 switch .text
1574 0278 _UART2_SmartCardNACKCmd:
1578 ; 429 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1580 ; 431 if (NewState != DISABLE)
1582 0278 4d tnz a
1583 0279 2706 jreq L556
1584 ; 434 UART2->CR5 |= UART2_CR5_NACK;
1586 027b 72185248 bset 21064,#4
1588 027f 2004 jra L756
1589 0281 L556:
1590 ; 439 UART2->CR5 &= ((u8)~(UART2_CR5_NACK));
1592 0281 72195248 bres 21064,#4
1593 0285 L756:
1594 ; 441 }
1597 0285 81 ret
1654 ; 450 void UART2_WakeUpConfig(UART2_WakeUp_TypeDef UART2_WakeUp)
1654 ; 451 {
1655 switch .text
1656 0286 _UART2_WakeUpConfig:
1660 ; 452 assert_param(IS_UART2_WAKEUP_OK(UART2_WakeUp));
1662 ; 454 UART2->CR1 &= ((u8)~UART2_CR1_WAKE);
1664 0286 72175244 bres 21060,#3
1665 ; 455 UART2->CR1 |= (u8)UART2_WakeUp;
1667 028a ca5244 or a,21060
1668 028d c75244 ld 21060,a
1669 ; 456 }
1672 0290 81 ret
1708 ; 468 void UART2_ReceiverWakeUpCmd(FunctionalState NewState)
1708 ; 469 {
1709 switch .text
1710 0291 _UART2_ReceiverWakeUpCmd:
1714 ; 470 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1716 ; 472 if (NewState != DISABLE)
1718 0291 4d tnz a
1719 0292 2706 jreq L527
1720 ; 475 UART2->CR2 |= UART2_CR2_RWU;
1722 0294 72125245 bset 21061,#1
1724 0298 2004 jra L727
1725 029a L527:
1726 ; 480 UART2->CR2 &= ((u8)~UART2_CR2_RWU);
1728 029a 72135245 bres 21061,#1
1729 029e L727:
1730 ; 482 }
1733 029e 81 ret
1756 ; 493 u8 UART2_ReceiveData8(void)
1756 ; 494 {
1757 switch .text
1758 029f _UART2_ReceiveData8:
1762 ; 495 return ((u8)UART2->DR);
1764 029f c65241 ld a,21057
1767 02a2 81 ret
1790 ; 506 u16 UART2_ReceiveData9(void)
1790 ; 507 {
1791 switch .text
1792 02a3 _UART2_ReceiveData9:
1794 02a3 89 pushw x
1795 00000002 OFST: set 2
1798 ; 508 return (u16)((((u16)UART2->DR) | ((u16)(((u16)((u16)UART2->CR1 & (u16)UART2_CR1_R8)) << 1))) & ((u16)0x01FF));
1800 02a4 c65244 ld a,21060
1801 02a7 5f clrw x
1802 02a8 a480 and a,#128
1803 02aa 5f clrw x
1804 02ab 02 rlwa x,a
1805 02ac 58 sllw x
1806 02ad 1f01 ldw (OFST-1,sp),x
1807 02af c65241 ld a,21057
1808 02b2 5f clrw x
1809 02b3 97 ld xl,a
1810 02b4 01 rrwa x,a
1811 02b5 1a02 or a,(OFST+0,sp)
1812 02b7 01 rrwa x,a
1813 02b8 1a01 or a,(OFST-1,sp)
1814 02ba 01 rrwa x,a
1815 02bb 01 rrwa x,a
1816 02bc a4ff and a,#255
1817 02be 01 rrwa x,a
1818 02bf a401 and a,#1
1819 02c1 01 rrwa x,a
1822 02c2 5b02 addw sp,#2
1823 02c4 81 ret
1857 ; 522 void UART2_SendData8(u8 Data)
1857 ; 523 {
1858 switch .text
1859 02c5 _UART2_SendData8:
1861 02c5 88 push a
1862 00000000 OFST: set 0
1865 02c6 L177:
1866 ; 525 while(!(UART2->SR&UART2_SR_TXE));
1868 02c6 c65240 ld a,21056
1869 02c9 a580 bcp a,#128
1870 02cb 27f9 jreq L177
1871 ; 526 UART2->DR = Data;
1873 02cd 7b01 ld a,(OFST+1,sp)
1874 02cf c75241 ld 21057,a
1875 ; 527 }
1878 02d2 84 pop a
1879 02d3 81 ret
1913 ; 538 void UART2_SendData9(u16 Data)
1913 ; 539 {
1914 switch .text
1915 02d4 _UART2_SendData9:
1917 02d4 89 pushw x
1918 00000000 OFST: set 0
1921 ; 540 UART2->CR1 &= ((u8)~UART2_CR1_T8); /* Clear the transmit data bit 8 */
1923 02d5 721d5244 bres 21060,#6
1924 ; 541 UART2->CR1 |= (u8)(((u8)(Data >> 2)) & UART2_CR1_T8); /* Write the transmit data bit [8] */
1926 02d9 54 srlw x
1927 02da 54 srlw x
1928 02db 9f ld a,xl
1929 02dc a440 and a,#64
1930 02de ca5244 or a,21060
1931 02e1 c75244 ld 21060,a
1932 ; 542 UART2->DR = (u8)(Data); /* Write the transmit data bit [0:7] */
1934 02e4 7b02 ld a,(OFST+2,sp)
1935 02e6 c75241 ld 21057,a
1936 ; 544 }
1939 02e9 85 popw x
1940 02ea 81 ret
1963 ; 551 void UART2_SendBreak(void)
1963 ; 552 {
1964 switch .text
1965 02eb _UART2_SendBreak:
1969 ; 553 UART2->CR2 |= UART2_CR2_SBK;
1971 02eb 72105245 bset 21061,#0
1972 ; 554 }
1975 02ef 81 ret
2009 ; 563 void UART2_SetAddress(u8 UART2_Address)
2009 ; 564 {
2010 switch .text
2011 02f0 _UART2_SetAddress:
2013 02f0 88 push a
2014 00000000 OFST: set 0
2017 ; 566 assert_param(IS_UART2_ADDRESS_OK(UART2_Address));
2019 ; 569 UART2->CR4 &= ((u8)~UART2_CR4_ADD);
2021 02f1 c65247 ld a,21063
2022 02f4 a4f0 and a,#240
2023 02f6 c75247 ld 21063,a
2024 ; 571 UART2->CR4 |= UART2_Address;
2026 02f9 c65247 ld a,21063
2027 02fc 1a01 or a,(OFST+1,sp)
2028 02fe c75247 ld 21063,a
2029 ; 572 }
2032 0301 84 pop a
2033 0302 81 ret
2067 ; 583 void UART2_SetGuardTime(u8 UART2_GuardTime)
2067 ; 584 {
2068 switch .text
2069 0303 _UART2_SetGuardTime:
2073 ; 586 UART2->GTR = UART2_GuardTime;
2075 0303 c7524a ld 21066,a
2076 ; 587 }
2079 0306 81 ret
2113 ; 613 void UART2_SetPrescaler(u8 UART2_Prescaler)
2113 ; 614 {
2114 switch .text
2115 0307 _UART2_SetPrescaler:
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