📄 stm8s_uart2.ls
字号:
1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.9.2 - 29 Jun 2010
3 ; Generator V4.3.5 - 02 Jul 2010
54 ; 48 void UART2_DeInit(void)
54 ; 49 {
56 switch .text
57 0000 _UART2_DeInit:
59 0000 88 push a
60 00000001 OFST: set 1
63 ; 50 u8 dummy = 0;
65 ; 53 dummy = UART2->SR;
67 0001 c65240 ld a,21056
68 ; 54 dummy = UART2->DR;
70 0004 c65241 ld a,21057
71 ; 56 UART2->BRR2 = UART2_BRR2_RESET_VALUE; /*< Set UART2_BRR2 to reset value 0x00 */
73 0007 725f5243 clr 21059
74 ; 57 UART2->BRR1 = UART2_BRR1_RESET_VALUE; /*< Set UART2_BRR1 to reset value 0x00 */
76 000b 725f5242 clr 21058
77 ; 59 UART2->CR1 = UART2_CR1_RESET_VALUE; /*< Set UART2_CR1 to reset value 0x00 */
79 000f 725f5244 clr 21060
80 ; 60 UART2->CR2 = UART2_CR2_RESET_VALUE; /*< Set UART2_CR2 to reset value 0x00 */
82 0013 725f5245 clr 21061
83 ; 61 UART2->CR3 = UART2_CR3_RESET_VALUE; /*< Set UART2_CR3 to reset value 0x00 */
85 0017 725f5246 clr 21062
86 ; 62 UART2->CR4 = UART2_CR4_RESET_VALUE; /*< Set UART2_CR4 to reset value 0x00 */
88 001b 725f5247 clr 21063
89 ; 63 UART2->CR5 = UART2_CR5_RESET_VALUE; /*< Set UART2_CR5 to reset value 0x00 */
91 001f 725f5248 clr 21064
92 ; 64 UART2->CR6 = UART2_CR6_RESET_VALUE; /*< Set UART2_CR6 to reset value 0x00 */
94 0023 725f5249 clr 21065
95 ; 66 }
98 0027 84 pop a
99 0028 81 ret
420 .const: section .text
421 0000 L01:
422 0000 00000064 dc.l 100
423 ; 78 void UART2_Init(u32 BaudRate, UART2_WordLength_TypeDef WordLength, UART2_StopBits_TypeDef StopBits, UART2_Parity_TypeDef Parity, UART2_SyncMode_TypeDef SyncMode, UART2_Mode_TypeDef Mode)
423 ; 79 {
424 switch .text
425 0029 _UART2_Init:
427 0029 520e subw sp,#14
428 0000000e OFST: set 14
431 ; 80 u8 BRR2_1, BRR2_2 = 0;
433 ; 81 u32 BaudRate_Mantissa, BaudRate_Mantissa100 = 0;
435 ; 84 assert_param(IS_UART2_BAUDRATE_OK(BaudRate));
437 ; 86 assert_param(IS_UART2_WORDLENGTH_OK(WordLength));
439 ; 88 assert_param(IS_UART2_STOPBITS_OK(StopBits));
441 ; 90 assert_param(IS_UART2_PARITY_OK(Parity));
443 ; 93 assert_param(IS_UART2_MODE_OK((u8)Mode));
445 ; 97 assert_param(IS_UART2_SYNCMODE_OK((u8)SyncMode));
447 ; 99 UART2->CR1 &= (u8)(~UART2_CR1_M); /**< Clear the word length bit */
449 002b 72195244 bres 21060,#4
450 ; 100 UART2->CR1 |= (u8)WordLength; /**< Set the word length bit according to UART2_WordLength value */
452 002f c65244 ld a,21060
453 0032 1a15 or a,(OFST+7,sp)
454 0034 c75244 ld 21060,a
455 ; 102 UART2->CR3 &= (u8)(~UART2_CR3_STOP); /**< Clear the STOP bits */
457 0037 c65246 ld a,21062
458 003a a4cf and a,#207
459 003c c75246 ld 21062,a
460 ; 103 UART2->CR3 |= (u8)StopBits; /**< Set the STOP bits number according to UART2_StopBits value */
462 003f c65246 ld a,21062
463 0042 1a16 or a,(OFST+8,sp)
464 0044 c75246 ld 21062,a
465 ; 105 UART2->CR1 &= (u8)(~(UART2_CR1_PCEN | UART2_CR1_PS )); /**< Clear the Parity Control bit */
467 0047 c65244 ld a,21060
468 004a a4f9 and a,#249
469 004c c75244 ld 21060,a
470 ; 106 UART2->CR1 |= (u8)Parity; /**< Set the Parity Control bit to UART2_Parity value */
472 004f c65244 ld a,21060
473 0052 1a17 or a,(OFST+9,sp)
474 0054 c75244 ld 21060,a
475 ; 108 UART2->BRR1 &= (u8)(~UART2_BRR1_DIVM); /**< Clear the LSB mantissa of UARTDIV */
477 0057 725f5242 clr 21058
478 ; 109 UART2->BRR2 &= (u8)(~UART2_BRR2_DIVM); /**< Clear the MSB mantissa of UARTDIV */
480 005b c65243 ld a,21059
481 005e a40f and a,#15
482 0060 c75243 ld 21059,a
483 ; 110 UART2->BRR2 &= (u8)(~UART2_BRR2_DIVF); /**< Clear the Fraction bits of UARTDIV */
485 0063 c65243 ld a,21059
486 0066 a4f0 and a,#240
487 0068 c75243 ld 21059,a
488 ; 113 BaudRate_Mantissa = ((u32)CLK_GetClockFreq() / (BaudRate << 4));
490 006b 96 ldw x,sp
491 006c 1c0011 addw x,#OFST+3
492 006f cd0000 call c_ltor
494 0072 a604 ld a,#4
495 0074 cd0000 call c_llsh
497 0077 96 ldw x,sp
498 0078 1c0001 addw x,#OFST-13
499 007b cd0000 call c_rtol
501 007e cd0000 call _CLK_GetClockFreq
503 0081 96 ldw x,sp
504 0082 1c0001 addw x,#OFST-13
505 0085 cd0000 call c_ludv
507 0088 96 ldw x,sp
508 0089 1c000b addw x,#OFST-3
509 008c cd0000 call c_rtol
511 ; 114 BaudRate_Mantissa100 = (((u32)CLK_GetClockFreq() * 100) / (BaudRate << 4));
513 008f 96 ldw x,sp
514 0090 1c0011 addw x,#OFST+3
515 0093 cd0000 call c_ltor
517 0096 a604 ld a,#4
518 0098 cd0000 call c_llsh
520 009b 96 ldw x,sp
521 009c 1c0001 addw x,#OFST-13
522 009f cd0000 call c_rtol
524 00a2 cd0000 call _CLK_GetClockFreq
526 00a5 a664 ld a,#100
527 00a7 cd0000 call c_smul
529 00aa 96 ldw x,sp
530 00ab 1c0001 addw x,#OFST-13
531 00ae cd0000 call c_ludv
533 00b1 96 ldw x,sp
534 00b2 1c0007 addw x,#OFST-7
535 00b5 cd0000 call c_rtol
537 ; 116 BRR2_1 = (u8)((u8)(((BaudRate_Mantissa100 - (BaudRate_Mantissa * 100))
537 ; 117 << 4) / 100) & (u8)0x0F); /**< Set the fraction of UARTDIV */
539 00b8 96 ldw x,sp
540 00b9 1c000b addw x,#OFST-3
541 00bc cd0000 call c_ltor
543 00bf a664 ld a,#100
544 00c1 cd0000 call c_smul
546 00c4 96 ldw x,sp
547 00c5 1c0001 addw x,#OFST-13
548 00c8 cd0000 call c_rtol
550 00cb 96 ldw x,sp
551 00cc 1c0007 addw x,#OFST-7
552 00cf cd0000 call c_ltor
554 00d2 96 ldw x,sp
555 00d3 1c0001 addw x,#OFST-13
556 00d6 cd0000 call c_lsub
558 00d9 a604 ld a,#4
559 00db cd0000 call c_llsh
561 00de ae0000 ldw x,#L01
562 00e1 cd0000 call c_ludv
564 00e4 b603 ld a,c_lreg+3
565 00e6 a40f and a,#15
566 00e8 6b05 ld (OFST-9,sp),a
567 ; 118 BRR2_2 = (u8)((BaudRate_Mantissa >> 4) & (u8)0xF0);
569 00ea 96 ldw x,sp
570 00eb 1c000b addw x,#OFST-3
571 00ee cd0000 call c_ltor
573 00f1 a604 ld a,#4
574 00f3 cd0000 call c_lursh
576 00f6 b603 ld a,c_lreg+3
577 00f8 a4f0 and a,#240
578 00fa b703 ld c_lreg+3,a
579 00fc 3f02 clr c_lreg+2
580 00fe 3f01 clr c_lreg+1
581 0100 3f00 clr c_lreg
582 0102 b603 ld a,c_lreg+3
583 0104 6b06 ld (OFST-8,sp),a
584 ; 120 UART2->BRR2 = (u8)(BRR2_1 | BRR2_2);
586 0106 7b05 ld a,(OFST-9,sp)
587 0108 1a06 or a,(OFST-8,sp)
588 010a c75243 ld 21059,a
589 ; 121 UART2->BRR1 = (u8)BaudRate_Mantissa; /**< Set the LSB mantissa of UARTDIV */
591 010d 7b0e ld a,(OFST+0,sp)
592 010f c75242 ld 21058,a
593 ; 123 UART2->CR2 &= (u8)~(UART2_CR2_TEN | UART2_CR2_REN); /**< Disable the Transmitter and Receiver before seting the LBCL, CPOL and CPHA bits */
595 0112 c65245 ld a,21061
596 0115 a4f3 and a,#243
597 0117 c75245 ld 21061,a
598 ; 124 UART2->CR3 &= (u8)~(UART2_CR3_CPOL | UART2_CR3_CPHA | UART2_CR3_LBCL); /**< Clear the Clock Polarity, lock Phase, Last Bit Clock pulse */
600 011a c65246 ld a,21062
601 011d a4f8 and a,#248
602 011f c75246 ld 21062,a
603 ; 125 UART2->CR3 |= (u8)((u8)SyncMode & (u8)(UART2_CR3_CPOL | UART2_CR3_CPHA | UART2_CR3_LBCL)); /**< Set the Clock Polarity, lock Phase, Last Bit Clock pulse */
605 0122 7b18 ld a,(OFST+10,sp)
606 0124 a407 and a,#7
607 0126 ca5246 or a,21062
608 0129 c75246 ld 21062,a
609 ; 127 if ((u8)Mode & (u8)UART2_MODE_TX_ENABLE)
611 012c 7b19 ld a,(OFST+11,sp)
612 012e a504 bcp a,#4
613 0130 2706 jreq L112
614 ; 129 UART2->CR2 |= (u8)UART2_CR2_TEN; /**< Set the Transmitter Enable bit */
616 0132 72165245 bset 21061,#3
618 0136 2004 jra L312
619 0138 L112:
620 ; 133 UART2->CR2 &= (u8)(~UART2_CR2_TEN); /**< Clear the Transmitter Disable bit */
622 0138 72175245 bres 21061,#3
623 013c L312:
624 ; 135 if ((u8)Mode & (u8)UART2_MODE_RX_ENABLE)
626 013c 7b19 ld a,(OFST+11,sp)
627 013e a508 bcp a,#8
628 0140 2706 jreq L512
629 ; 137 UART2->CR2 |= (u8)UART2_CR2_REN; /**< Set the Receiver Enable bit */
631 0142 72145245 bset 21061,#2
633 0146 2004 jra L712
634 0148 L512:
635 ; 141 UART2->CR2 &= (u8)(~UART2_CR2_REN); /**< Clear the Receiver Disable bit */
637 0148 72155245 bres 21061,#2
638 014c L712:
639 ; 144 if ((u8)SyncMode&(u8)UART2_SYNCMODE_CLOCK_DISABLE)
641 014c 7b18 ld a,(OFST+10,sp)
642 014e a580 bcp a,#128
643 0150 2706 jreq L122
644 ; 146 UART2->CR3 &= (u8)(~UART2_CR3_CKEN); /**< Clear the Clock Enable bit */
646 0152 72175246 bres 21062,#3
648 0156 200a jra L322
649 0158 L122:
650 ; 151 UART2->CR3 |= (u8)((u8)SyncMode & UART2_CR3_CKEN);
652 0158 7b18 ld a,(OFST+10,sp)
653 015a a408 and a,#8
654 015c ca5246 or a,21062
655 015f c75246 ld 21062,a
656 0162 L322:
657 ; 153 }
660 0162 5b0e addw sp,#14
661 0164 81 ret
716 ; 164 void UART2_Cmd(FunctionalState NewState)
716 ; 165 {
717 switch .text
718 0165 _UART2_Cmd:
722 ; 167 if (NewState != DISABLE)
724 0165 4d tnz a
725 0166 2706 jreq L352
726 ; 169 UART2->CR1 &= (u8)(~UART2_CR1_UARTD); /**< UART2 Enable */
728 0168 721b5244 bres 21060,#5
730 016c 2004 jra L552
731 016e L352:
732 ; 173 UART2->CR1 |= UART2_CR1_UARTD; /**< UART2 Disable (for low power consumption) */
734 016e 721a5244 bset 21060,#5
735 0172 L552:
736 ; 175 }
739 0172 81 ret
871 ; 194 void UART2_ITConfig(UART2_IT_TypeDef UART2_IT, FunctionalState NewState)
871 ; 195 {
872 switch .text
873 0173 _UART2_ITConfig:
875 0173 89 pushw x
876 0174 89 pushw x
877 00000002 OFST: set 2
880 ; 196 u8 uartreg, itpos = 0x00;
882 ; 197 assert_param(IS_UART2_CONFIG_IT_OK(UART2_IT));
884 ; 198 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
886 ; 201 uartreg = (u8)(UART2_IT >> 0x08);
888 0175 9e ld a,xh
889 0176 6b01 ld (OFST-1,sp),a
890 ; 204 itpos = (u8)((u8)1 << (u8)((u8)UART2_IT & (u8)0x0F));
892 0178 9f ld a,xl
893 0179 a40f and a,#15
894 017b 5f clrw x
895 017c 97 ld xl,a
896 017d a601 ld a,#1
897 017f 5d tnzw x
898 0180 2704 jreq L61
899 0182 L02:
900 0182 48 sll a
901 0183 5a decw x
902 0184 26fc jrne L02
903 0186 L61:
904 0186 6b02 ld (OFST+0,sp),a
905 ; 206 if (NewState != DISABLE)
907 0188 0d07 tnz (OFST+5,sp)
908 018a 273a jreq L733
909 ; 209 if (uartreg == 0x01)
911 018c 7b01 ld a,(OFST-1,sp)
912 018e a101 cp a,#1
913 0190 260a jrne L143
914 ; 211 UART2->CR1 |= itpos;
916 0192 c65244 ld a,21060
917 0195 1a02 or a,(OFST+0,sp)
918 0197 c75244 ld 21060,a
920 019a 2066 jra L553
921 019c L143:
922 ; 213 else if (uartreg == 0x02)
924 019c 7b01 ld a,(OFST-1,sp)
925 019e a102 cp a,#2
926 01a0 260a jrne L543
927 ; 215 UART2->CR2 |= itpos;
929 01a2 c65245 ld a,21061
930 01a5 1a02 or a,(OFST+0,sp)
931 01a7 c75245 ld 21061,a
933 01aa 2056 jra L553
934 01ac L543:
935 ; 217 else if (uartreg == 0x03)
937 01ac 7b01 ld a,(OFST-1,sp)
938 01ae a103 cp a,#3
939 01b0 260a jrne L153
940 ; 219 UART2->CR4 |= itpos;
942 01b2 c65247 ld a,21063
943 01b5 1a02 or a,(OFST+0,sp)
944 01b7 c75247 ld 21063,a
946 01ba 2046 jra L553
947 01bc L153:
948 ; 223 UART2->CR6 |= itpos;
950 01bc c65249 ld a,21065
951 01bf 1a02 or a,(OFST+0,sp)
952 01c1 c75249 ld 21065,a
953 01c4 203c jra L553
954 01c6 L733:
955 ; 229 if (uartreg == 0x01)
957 01c6 7b01 ld a,(OFST-1,sp)
958 01c8 a101 cp a,#1
959 01ca 260b jrne L753
960 ; 231 UART2->CR1 &= (u8)(~itpos);
962 01cc 7b02 ld a,(OFST+0,sp)
963 01ce 43 cpl a
964 01cf c45244 and a,21060
965 01d2 c75244 ld 21060,a
967 01d5 202b jra L553
968 01d7 L753:
969 ; 233 else if (uartreg == 0x02)
971 01d7 7b01 ld a,(OFST-1,sp)
972 01d9 a102 cp a,#2
973 01db 260b jrne L363
974 ; 235 UART2->CR2 &= (u8)(~itpos);
976 01dd 7b02 ld a,(OFST+0,sp)
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