📄 stm8s_clk.ls
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1941 ; 580 CLK->CSSR |= CLK_CSSR_CSSEN;
1943 0250 721050c8 bset 20680,#0
1944 ; 581 }
1947 0254 81 ret
1972 ; 590 CLK_Source_TypeDef CLK_GetSYSCLKSource(void)
1972 ; 591 {
1973 switch .text
1974 0255 _CLK_GetSYSCLKSource:
1978 ; 592 return((CLK_Source_TypeDef)CLK->CMSR);
1980 0255 c650c3 ld a,20675
1983 0258 81 ret
2046 ; 602 u32 CLK_GetClockFreq(void)
2046 ; 603 {
2047 switch .text
2048 0259 _CLK_GetClockFreq:
2050 0259 5209 subw sp,#9
2051 00000009 OFST: set 9
2054 ; 605 u32 clockfrequency = 0;
2056 ; 606 CLK_Source_TypeDef clocksource = CLK_SOURCE_HSI;
2058 ; 607 u8 tmp = 0, presc = 0;
2062 ; 610 clocksource = (CLK_Source_TypeDef)CLK->CMSR;
2064 025b c650c3 ld a,20675
2065 025e 6b09 ld (OFST+0,sp),a
2066 ; 612 if (clocksource == CLK_SOURCE_HSI)
2068 0260 7b09 ld a,(OFST+0,sp)
2069 0262 a1e1 cp a,#225
2070 0264 2641 jrne L1111
2071 ; 614 tmp = (u8)(CLK->CKDIVR & CLK_CKDIVR_HSIDIV);
2073 0266 c650c6 ld a,20678
2074 0269 a418 and a,#24
2075 026b 6b09 ld (OFST+0,sp),a
2076 ; 615 tmp = (u8)(tmp >> 3);
2078 026d 0409 srl (OFST+0,sp)
2079 026f 0409 srl (OFST+0,sp)
2080 0271 0409 srl (OFST+0,sp)
2081 ; 616 presc = HSIDivFactor[tmp];
2083 0273 7b09 ld a,(OFST+0,sp)
2084 0275 5f clrw x
2085 0276 97 ld xl,a
2086 0277 d60000 ld a,(_HSIDivFactor,x)
2087 027a 6b09 ld (OFST+0,sp),a
2088 ; 617 clockfrequency = HSI_VALUE / presc;
2090 027c 7b09 ld a,(OFST+0,sp)
2091 027e b703 ld c_lreg+3,a
2092 0280 3f02 clr c_lreg+2
2093 0282 3f01 clr c_lreg+1
2094 0284 3f00 clr c_lreg
2095 0286 96 ldw x,sp
2096 0287 1c0001 addw x,#OFST-8
2097 028a cd0000 call c_rtol
2099 028d ae2400 ldw x,#9216
2100 0290 bf02 ldw c_lreg+2,x
2101 0292 ae00f4 ldw x,#244
2102 0295 bf00 ldw c_lreg,x
2103 0297 96 ldw x,sp
2104 0298 1c0001 addw x,#OFST-8
2105 029b cd0000 call c_ludv
2107 029e 96 ldw x,sp
2108 029f 1c0005 addw x,#OFST-4
2109 02a2 cd0000 call c_rtol
2112 02a5 201c jra L3111
2113 02a7 L1111:
2114 ; 619 else if ( clocksource == CLK_SOURCE_LSI)
2116 02a7 7b09 ld a,(OFST+0,sp)
2117 02a9 a1d2 cp a,#210
2118 02ab 260c jrne L5111
2119 ; 621 clockfrequency = LSI_VALUE;
2121 02ad aef400 ldw x,#62464
2122 02b0 1f07 ldw (OFST-2,sp),x
2123 02b2 ae0001 ldw x,#1
2124 02b5 1f05 ldw (OFST-4,sp),x
2126 02b7 200a jra L3111
2127 02b9 L5111:
2128 ; 626 clockfrequency = 16000000;
2130 02b9 ae2400 ldw x,#9216
2131 02bc 1f07 ldw (OFST-2,sp),x
2132 02be ae00f4 ldw x,#244
2133 02c1 1f05 ldw (OFST-4,sp),x
2134 02c3 L3111:
2135 ; 629 return((u32)clockfrequency);
2137 02c3 96 ldw x,sp
2138 02c4 1c0005 addw x,#OFST-4
2139 02c7 cd0000 call c_ltor
2143 02ca 5b09 addw sp,#9
2144 02cc 81 ret
2243 ; 640 void CLK_AdjustHSICalibrationValue(CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)
2243 ; 641 {
2244 switch .text
2245 02cd _CLK_AdjustHSICalibrationValue:
2247 02cd 88 push a
2248 00000000 OFST: set 0
2251 ; 644 assert_param(IS_CLK_HSITRIMVALUE_OK(CLK_HSICalibrationValue));
2253 ; 647 CLK->HSITRIMR = (u8)((CLK->HSITRIMR & (u8)(~CLK_HSITRIMR_HSITRIM))|((u8)CLK_HSICalibrationValue));
2255 02ce c650cc ld a,20684
2256 02d1 a4f8 and a,#248
2257 02d3 1a01 or a,(OFST+1,sp)
2258 02d5 c750cc ld 20684,a
2259 ; 649 }
2262 02d8 84 pop a
2263 02d9 81 ret
2287 ; 661 void CLK_SYSCLKEmergencyClear(void)
2287 ; 662 {
2288 switch .text
2289 02da _CLK_SYSCLKEmergencyClear:
2293 ; 663 CLK->SWCR &= (u8)(~CLK_SWCR_SWBSY);
2295 02da 721150c5 bres 20677,#0
2296 ; 664 }
2299 02de 81 ret
2452 ; 673 FlagStatus CLK_GetFlagStatus(CLK_Flag_TypeDef CLK_FLAG)
2452 ; 674 {
2453 switch .text
2454 02df _CLK_GetFlagStatus:
2456 02df 89 pushw x
2457 02e0 5203 subw sp,#3
2458 00000003 OFST: set 3
2461 ; 676 u16 statusreg = 0;
2463 ; 677 u8 tmpreg = 0;
2465 ; 678 FlagStatus bitstatus = RESET;
2467 ; 681 assert_param(IS_CLK_FLAG_OK(CLK_FLAG));
2469 ; 684 statusreg = (u16)((u16)CLK_FLAG & (u16)0xFF00);
2471 02e2 01 rrwa x,a
2472 02e3 9f ld a,xl
2473 02e4 a4ff and a,#255
2474 02e6 97 ld xl,a
2475 02e7 4f clr a
2476 02e8 02 rlwa x,a
2477 02e9 1f01 ldw (OFST-2,sp),x
2478 02eb 01 rrwa x,a
2479 ; 687 if (statusreg == 0x0100) /* The flag to check is in ICKRregister */
2481 02ec 1e01 ldw x,(OFST-2,sp)
2482 02ee a30100 cpw x,#256
2483 02f1 2607 jrne L3621
2484 ; 689 tmpreg = CLK->ICKR;
2486 02f3 c650c0 ld a,20672
2487 02f6 6b03 ld (OFST+0,sp),a
2489 02f8 202f jra L5621
2490 02fa L3621:
2491 ; 691 else if (statusreg == 0x0200) /* The flag to check is in ECKRregister */
2493 02fa 1e01 ldw x,(OFST-2,sp)
2494 02fc a30200 cpw x,#512
2495 02ff 2607 jrne L7621
2496 ; 693 tmpreg = CLK->ECKR;
2498 0301 c650c1 ld a,20673
2499 0304 6b03 ld (OFST+0,sp),a
2501 0306 2021 jra L5621
2502 0308 L7621:
2503 ; 695 else if (statusreg == 0x0300) /* The flag to check is in SWIC register */
2505 0308 1e01 ldw x,(OFST-2,sp)
2506 030a a30300 cpw x,#768
2507 030d 2607 jrne L3721
2508 ; 697 tmpreg = CLK->SWCR;
2510 030f c650c5 ld a,20677
2511 0312 6b03 ld (OFST+0,sp),a
2513 0314 2013 jra L5621
2514 0316 L3721:
2515 ; 699 else if (statusreg == 0x0400) /* The flag to check is in CSS register */
2517 0316 1e01 ldw x,(OFST-2,sp)
2518 0318 a30400 cpw x,#1024
2519 031b 2607 jrne L7721
2520 ; 701 tmpreg = CLK->CSSR;
2522 031d c650c8 ld a,20680
2523 0320 6b03 ld (OFST+0,sp),a
2525 0322 2005 jra L5621
2526 0324 L7721:
2527 ; 705 tmpreg = CLK->CCOR;
2529 0324 c650c9 ld a,20681
2530 0327 6b03 ld (OFST+0,sp),a
2531 0329 L5621:
2532 ; 708 if ((tmpreg & (u8)CLK_FLAG) != (u8)RESET)
2534 0329 7b05 ld a,(OFST+2,sp)
2535 032b 1503 bcp a,(OFST+0,sp)
2536 032d 2706 jreq L3031
2537 ; 710 bitstatus = SET;
2539 032f a601 ld a,#1
2540 0331 6b03 ld (OFST+0,sp),a
2542 0333 2002 jra L5031
2543 0335 L3031:
2544 ; 714 bitstatus = RESET;
2546 0335 0f03 clr (OFST+0,sp)
2547 0337 L5031:
2548 ; 718 return((FlagStatus)bitstatus);
2550 0337 7b03 ld a,(OFST+0,sp)
2553 0339 5b05 addw sp,#5
2554 033b 81 ret
2600 ; 728 ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT)
2600 ; 729 {
2601 switch .text
2602 033c _CLK_GetITStatus:
2604 033c 88 push a
2605 033d 88 push a
2606 00000001 OFST: set 1
2609 ; 731 ITStatus bitstatus = RESET;
2611 ; 734 assert_param(IS_CLK_IT_OK(CLK_IT));
2613 ; 736 if (CLK_IT == CLK_IT_SWIF)
2615 033e a11c cp a,#28
2616 0340 2611 jrne L1331
2617 ; 739 if ((CLK->SWCR & (u8)CLK_IT) == (u8)0x0C)
2619 0342 c450c5 and a,20677
2620 0345 a10c cp a,#12
2621 0347 2606 jrne L3331
2622 ; 741 bitstatus = SET;
2624 0349 a601 ld a,#1
2625 034b 6b01 ld (OFST+0,sp),a
2627 034d 2015 jra L7331
2628 034f L3331:
2629 ; 745 bitstatus = RESET;
2631 034f 0f01 clr (OFST+0,sp)
2632 0351 2011 jra L7331
2633 0353 L1331:
2634 ; 751 if ((CLK->CSSR & (u8)CLK_IT) == (u8)0x0C)
2636 0353 c650c8 ld a,20680
2637 0356 1402 and a,(OFST+1,sp)
2638 0358 a10c cp a,#12
2639 035a 2606 jrne L1431
2640 ; 753 bitstatus = SET;
2642 035c a601 ld a,#1
2643 035e 6b01 ld (OFST+0,sp),a
2645 0360 2002 jra L7331
2646 0362 L1431:
2647 ; 757 bitstatus = RESET;
2649 0362 0f01 clr (OFST+0,sp)
2650 0364 L7331:
2651 ; 762 return bitstatus;
2653 0364 7b01 ld a,(OFST+0,sp)
2656 0366 85 popw x
2657 0367 81 ret
2693 ; 772 void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT)
2693 ; 773 {
2694 switch .text
2695 0368 _CLK_ClearITPendingBit:
2699 ; 776 assert_param(IS_CLK_IT_OK(CLK_IT));
2701 ; 778 if (CLK_IT == (u8)CLK_IT_CSSD)
2703 0368 a10c cp a,#12
2704 036a 2606 jrne L3631
2705 ; 781 CLK->CSSR &= (u8)(~CLK_CSSR_CSSD);
2707 036c 721750c8 bres 20680,#3
2709 0370 2004 jra L5631
2710 0372 L3631:
2711 ; 786 CLK->SWCR &= (u8)(~CLK_SWCR_SWIF);
2713 0372 721750c5 bres 20677,#3
2714 0376 L5631:
2715 ; 789 }
2718 0376 81 ret
2753 xdef _CLKPrescTable
2754 xdef _HSIDivFactor
2755 xdef _CLK_ClearITPendingBit
2756 xdef _CLK_GetITStatus
2757 xdef _CLK_GetFlagStatus
2758 xdef _CLK_GetSYSCLKSource
2759 xdef _CLK_GetClockFreq
2760 xdef _CLK_AdjustHSICalibrationValue
2761 xdef _CLK_SYSCLKEmergencyClear
2762 xdef _CLK_ClockSecuritySystemEnable
2763 xdef _CLK_CANConfig
2764 xdef _CLK_SWIMConfig
2765 xdef _CLK_SYSCLKConfig
2766 xdef _CLK_ITConfig
2767 xdef _CLK_CCOConfig
2768 xdef _CLK_HSIPrescalerConfig
2769 xdef _CLK_ClockSwitchConfig
2770 xdef _CLK_PeripheralClockConfig
2771 xdef _CLK_SlowActiveHaltWakeUpCmd
2772 xdef _CLK_FastHaltWakeUpCmd
2773 xdef _CLK_ClockSwitchCmd
2774 xdef _CLK_CCOCmd
2775 xdef _CLK_LSICmd
2776 xdef _CLK_HSICmd
2777 xdef _CLK_HSECmd
2778 xdef _CLK_DeInit
2779 xref.b c_lreg
2780 xref.b c_x
2799 xref c_ltor
2800 xref c_ludv
2801 xref c_rtol
2802 end
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