📄 stm8s_clk.ls
字号:
1 ; C Compiler for STM8 (COSMIC Software)
2 ; Parser V4.9.2 - 29 Jun 2010
3 ; Generator V4.3.5 - 02 Jul 2010
15 .const: section .text
16 0000 _HSIDivFactor:
17 0000 01 dc.b 1
18 0001 02 dc.b 2
19 0002 04 dc.b 4
20 0003 08 dc.b 8
21 0004 _CLKPrescTable:
22 0004 01 dc.b 1
23 0005 02 dc.b 2
24 0006 04 dc.b 4
25 0007 08 dc.b 8
26 0008 0a dc.b 10
27 0009 10 dc.b 16
28 000a 14 dc.b 20
29 000b 28 dc.b 40
58 ; 64 void CLK_DeInit(void)
58 ; 65 {
60 switch .text
61 0000 _CLK_DeInit:
65 ; 67 CLK->ICKR = CLK_ICKR_RESET_VALUE;
67 0000 350150c0 mov 20672,#1
68 ; 68 CLK->ECKR = CLK_ECKR_RESET_VALUE;
70 0004 725f50c1 clr 20673
71 ; 69 CLK->SWR = CLK_SWR_RESET_VALUE;
73 0008 35e150c4 mov 20676,#225
74 ; 70 CLK->SWCR = CLK_SWCR_RESET_VALUE;
76 000c 725f50c5 clr 20677
77 ; 71 CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE;
79 0010 351850c6 mov 20678,#24
80 ; 72 CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE;
82 0014 35ff50c7 mov 20679,#255
83 ; 73 CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE;
85 0018 35ff50ca mov 20682,#255
86 ; 74 CLK->CSSR = CLK_CSSR_RESET_VALUE;
88 001c 725f50c8 clr 20680
89 ; 75 CLK->CCOR = CLK_CCOR_RESET_VALUE;
91 0020 725f50c9 clr 20681
93 0024 L52:
94 ; 76 while (CLK->CCOR & CLK_CCOR_CCOEN)
96 0024 c650c9 ld a,20681
97 0027 a501 bcp a,#1
98 0029 26f9 jrne L52
99 ; 78 CLK->CCOR = CLK_CCOR_RESET_VALUE;
101 002b 725f50c9 clr 20681
102 ; 79 CLK->CANCCR = CLK_CANCCR_RESET_VALUE;
104 002f 725f50cb clr 20683
105 ; 80 CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE;
107 0033 725f50cc clr 20684
108 ; 81 CLK->SWIMCCR = CLK_SWIMCCR_RESET_VALUE;
110 0037 725f50cd clr 20685
111 ; 83 }
114 003b 81 ret
170 ; 94 void CLK_FastHaltWakeUpCmd(FunctionalState NewState)
170 ; 95 {
171 switch .text
172 003c _CLK_FastHaltWakeUpCmd:
176 ; 98 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
178 ; 100 if (NewState != DISABLE)
180 003c 4d tnz a
181 003d 2706 jreq L75
182 ; 103 CLK->ICKR |= CLK_ICKR_FHWU;
184 003f 721450c0 bset 20672,#2
186 0043 2004 jra L16
187 0045 L75:
188 ; 108 CLK->ICKR &= (u8)(~CLK_ICKR_FHWU);
190 0045 721550c0 bres 20672,#2
191 0049 L16:
192 ; 111 }
195 0049 81 ret
230 ; 118 void CLK_HSECmd(FunctionalState NewState)
230 ; 119 {
231 switch .text
232 004a _CLK_HSECmd:
236 ; 122 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
238 ; 124 if (NewState != DISABLE)
240 004a 4d tnz a
241 004b 2706 jreq L101
242 ; 127 CLK->ECKR |= CLK_ECKR_HSEEN;
244 004d 721050c1 bset 20673,#0
246 0051 2004 jra L301
247 0053 L101:
248 ; 132 CLK->ECKR &= (u8)(~CLK_ECKR_HSEEN);
250 0053 721150c1 bres 20673,#0
251 0057 L301:
252 ; 135 }
255 0057 81 ret
290 ; 142 void CLK_HSICmd(FunctionalState NewState)
290 ; 143 {
291 switch .text
292 0058 _CLK_HSICmd:
296 ; 146 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
298 ; 148 if (NewState != DISABLE)
300 0058 4d tnz a
301 0059 2706 jreq L321
302 ; 151 CLK->ICKR |= CLK_ICKR_HSIEN;
304 005b 721050c0 bset 20672,#0
306 005f 2004 jra L521
307 0061 L321:
308 ; 156 CLK->ICKR &= (u8)(~CLK_ICKR_HSIEN);
310 0061 721150c0 bres 20672,#0
311 0065 L521:
312 ; 159 }
315 0065 81 ret
350 ; 166 void CLK_LSICmd(FunctionalState NewState)
350 ; 167 {
351 switch .text
352 0066 _CLK_LSICmd:
356 ; 170 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
358 ; 172 if (NewState != DISABLE)
360 0066 4d tnz a
361 0067 2706 jreq L541
362 ; 175 CLK->ICKR |= CLK_ICKR_LSIEN;
364 0069 721650c0 bset 20672,#3
366 006d 2004 jra L741
367 006f L541:
368 ; 180 CLK->ICKR &= (u8)(~CLK_ICKR_LSIEN);
370 006f 721750c0 bres 20672,#3
371 0073 L741:
372 ; 183 }
375 0073 81 ret
410 ; 191 void CLK_CCOCmd(FunctionalState NewState)
410 ; 192 {
411 switch .text
412 0074 _CLK_CCOCmd:
416 ; 195 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
418 ; 197 if (NewState != DISABLE)
420 0074 4d tnz a
421 0075 2706 jreq L761
422 ; 200 CLK->CCOR |= CLK_CCOR_CCOEN;
424 0077 721050c9 bset 20681,#0
426 007b 2004 jra L171
427 007d L761:
428 ; 205 CLK->CCOR &= (u8)(~CLK_CCOR_CCOEN);
430 007d 721150c9 bres 20681,#0
431 0081 L171:
432 ; 208 }
435 0081 81 ret
470 ; 217 void CLK_ClockSwitchCmd(FunctionalState NewState)
470 ; 218 {
471 switch .text
472 0082 _CLK_ClockSwitchCmd:
476 ; 221 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
478 ; 223 if (NewState != DISABLE )
480 0082 4d tnz a
481 0083 2706 jreq L112
482 ; 226 CLK->SWCR |= CLK_SWCR_SWEN;
484 0085 721250c5 bset 20677,#1
486 0089 2004 jra L312
487 008b L112:
488 ; 231 CLK->SWCR &= (u8)(~CLK_SWCR_SWEN);
490 008b 721350c5 bres 20677,#1
491 008f L312:
492 ; 234 }
495 008f 81 ret
531 ; 244 void CLK_SlowActiveHaltWakeUpCmd(FunctionalState NewState)
531 ; 245 {
532 switch .text
533 0090 _CLK_SlowActiveHaltWakeUpCmd:
537 ; 248 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
539 ; 250 if (NewState != DISABLE)
541 0090 4d tnz a
542 0091 2706 jreq L332
543 ; 253 CLK->ICKR |= CLK_ICKR_SWUAH;
545 0093 721a50c0 bset 20672,#5
547 0097 2004 jra L532
548 0099 L332:
549 ; 258 CLK->ICKR &= (u8)(~CLK_ICKR_SWUAH);
551 0099 721b50c0 bres 20672,#5
552 009d L532:
553 ; 261 }
556 009d 81 ret
715 ; 271 void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
715 ; 272 {
716 switch .text
717 009e _CLK_PeripheralClockConfig:
719 009e 89 pushw x
720 00000000 OFST: set 0
723 ; 275 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
725 ; 276 assert_param(IS_CLK_PERIPHERAL_OK(CLK_Peripheral));
727 ; 278 if (((u8)CLK_Peripheral & (u8)0x10) == 0x00)
729 009f 9e ld a,xh
730 00a0 a510 bcp a,#16
731 00a2 2633 jrne L123
732 ; 280 if (NewState != DISABLE)
734 00a4 0d02 tnz (OFST+2,sp)
735 00a6 2717 jreq L323
736 ; 283 CLK->PCKENR1 |= (u8)((u8)1 << ((u8)CLK_Peripheral & (u8)0x0F));
738 00a8 7b01 ld a,(OFST+1,sp)
739 00aa a40f and a,#15
740 00ac 5f clrw x
741 00ad 97 ld xl,a
742 00ae a601 ld a,#1
743 00b0 5d tnzw x
744 00b1 2704 jreq L62
745 00b3 L03:
746 00b3 48 sll a
747 00b4 5a decw x
748 00b5 26fc jrne L03
749 00b7 L62:
750 00b7 ca50c7 or a,20679
751 00ba c750c7 ld 20679,a
753 00bd 2049 jra L723
754 00bf L323:
755 ; 288 CLK->PCKENR1 &= (u8)(~(u8)(((u8)1 << ((u8)CLK_Peripheral & (u8)0x0F))));
757 00bf 7b01 ld a,(OFST+1,sp)
758 00c1 a40f and a,#15
759 00c3 5f clrw x
760 00c4 97 ld xl,a
761 00c5 a601 ld a,#1
762 00c7 5d tnzw x
763 00c8 2704 jreq L23
764 00ca L43:
765 00ca 48 sll a
766 00cb 5a decw x
767 00cc 26fc jrne L43
768 00ce L23:
769 00ce 43 cpl a
770 00cf c450c7 and a,20679
771 00d2 c750c7 ld 20679,a
772 00d5 2031 jra L723
773 00d7 L123:
774 ; 293 if (NewState != DISABLE)
776 00d7 0d02 tnz (OFST+2,sp)
777 00d9 2717 jreq L133
778 ; 296 CLK->PCKENR2 |= (u8)((u8)1 << ((u8)CLK_Peripheral & (u8)0x0F));
780 00db 7b01 ld a,(OFST+1,sp)
781 00dd a40f and a,#15
782 00df 5f clrw x
783 00e0 97 ld xl,a
784 00e1 a601 ld a,#1
785 00e3 5d tnzw x
786 00e4 2704 jreq L63
787 00e6 L04:
788 00e6 48 sll a
789 00e7 5a decw x
790 00e8 26fc jrne L04
791 00ea L63:
792 00ea ca50ca or a,20682
793 00ed c750ca ld 20682,a
795 00f0 2016 jra L723
796 00f2 L133:
797 ; 301 CLK->PCKENR2 &= (u8)(~(u8)(((u8)1 << ((u8)CLK_Peripheral & (u8)0x0F))));
799 00f2 7b01 ld a,(OFST+1,sp)
800 00f4 a40f and a,#15
801 00f6 5f clrw x
802 00f7 97 ld xl,a
803 00f8 a601 ld a,#1
804 00fa 5d tnzw x
805 00fb 2704 jreq L24
806 00fd L44:
807 00fd 48 sll a
808 00fe 5a decw x
809 00ff 26fc jrne L44
810 0101 L24:
811 0101 43 cpl a
812 0102 c450ca and a,20682
813 0105 c750ca ld 20682,a
814 0108 L723:
815 ; 305 }
818 0108 85 popw x
819 0109 81 ret
1007 ; 318 ErrorStatus CLK_ClockSwitchConfig(CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState)
1007 ; 319 {
1008 switch .text
1009 010a _CLK_ClockSwitchConfig:
1011 010a 89 pushw x
1012 010b 5204 subw sp,#4
1013 00000004 OFST: set 4
1016 ; 322 u16 DownCounter = CLK_TIMEOUT;
1018 010d ae0491 ldw x,#1169
1019 0110 1f03 ldw (OFST-1,sp),x
1020 ; 323 ErrorStatus Swif = ERROR;
1022 ; 326 assert_param(IS_CLK_SOURCE_OK(CLK_NewClock));
1024 ; 327 assert_param(IS_CLK_SWITCHMODE_OK(CLK_SwitchMode));
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