📄 stm8s_clk.ls
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1026 ; 328 assert_param(IS_FUNCTIONALSTATE_OK(ITState));
1028 ; 329 assert_param(IS_CLK_CURRENTCLOCKSTATE_OK(CLK_CurrentClockState));
1030 ; 332 clock_master = (CLK_Source_TypeDef)CLK->CMSR;
1032 0112 c650c3 ld a,20675
1033 0115 6b01 ld (OFST-3,sp),a
1034 ; 335 if (CLK_SwitchMode == CLK_SWITCHMODE_AUTO)
1036 0117 7b05 ld a,(OFST+1,sp)
1037 0119 a101 cp a,#1
1038 011b 2639 jrne L544
1039 ; 339 CLK->SWCR |= CLK_SWCR_SWEN;
1041 011d 721250c5 bset 20677,#1
1042 ; 342 if (ITState != DISABLE)
1044 0121 0d09 tnz (OFST+5,sp)
1045 0123 2706 jreq L744
1046 ; 344 CLK->SWCR |= CLK_SWCR_SWIEN;
1048 0125 721450c5 bset 20677,#2
1050 0129 2004 jra L154
1051 012b L744:
1052 ; 348 CLK->SWCR &= (u8)(~CLK_SWCR_SWIEN);
1054 012b 721550c5 bres 20677,#2
1055 012f L154:
1056 ; 352 CLK->SWR = (u8)CLK_NewClock;
1058 012f 7b06 ld a,(OFST+2,sp)
1059 0131 c750c4 ld 20676,a
1061 0134 2007 jra L754
1062 0136 L354:
1063 ; 356 DownCounter--;
1065 0136 1e03 ldw x,(OFST-1,sp)
1066 0138 1d0001 subw x,#1
1067 013b 1f03 ldw (OFST-1,sp),x
1068 013d L754:
1069 ; 354 while (((CLK->SWCR & CLK_SWCR_SWBSY) && (DownCounter != 0)))
1071 013d c650c5 ld a,20677
1072 0140 a501 bcp a,#1
1073 0142 2704 jreq L364
1075 0144 1e03 ldw x,(OFST-1,sp)
1076 0146 26ee jrne L354
1077 0148 L364:
1078 ; 359 if (DownCounter != 0)
1080 0148 1e03 ldw x,(OFST-1,sp)
1081 014a 2706 jreq L564
1082 ; 361 Swif = SUCCESS;
1084 014c a601 ld a,#1
1085 014e 6b02 ld (OFST-2,sp),a
1087 0150 201b jra L174
1088 0152 L564:
1089 ; 365 Swif = ERROR;
1091 0152 0f02 clr (OFST-2,sp)
1092 0154 2017 jra L174
1093 0156 L544:
1094 ; 373 if (ITState != DISABLE)
1096 0156 0d09 tnz (OFST+5,sp)
1097 0158 2706 jreq L374
1098 ; 375 CLK->SWCR |= CLK_SWCR_SWIEN;
1100 015a 721450c5 bset 20677,#2
1102 015e 2004 jra L574
1103 0160 L374:
1104 ; 379 CLK->SWCR &= (u8)(~CLK_SWCR_SWIEN);
1106 0160 721550c5 bres 20677,#2
1107 0164 L574:
1108 ; 383 CLK->SWR = (u8)CLK_NewClock;
1110 0164 7b06 ld a,(OFST+2,sp)
1111 0166 c750c4 ld 20676,a
1112 ; 387 Swif = SUCCESS;
1114 0169 a601 ld a,#1
1115 016b 6b02 ld (OFST-2,sp),a
1116 016d L174:
1117 ; 392 if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSI))
1119 016d 0d0a tnz (OFST+6,sp)
1120 016f 260c jrne L774
1122 0171 7b01 ld a,(OFST-3,sp)
1123 0173 a1e1 cp a,#225
1124 0175 2606 jrne L774
1125 ; 394 CLK->ICKR &= (u8)(~CLK_ICKR_HSIEN);
1127 0177 721150c0 bres 20672,#0
1129 017b 201e jra L105
1130 017d L774:
1131 ; 396 else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_LSI))
1133 017d 0d0a tnz (OFST+6,sp)
1134 017f 260c jrne L305
1136 0181 7b01 ld a,(OFST-3,sp)
1137 0183 a1d2 cp a,#210
1138 0185 2606 jrne L305
1139 ; 398 CLK->ICKR &= (u8)(~CLK_ICKR_LSIEN);
1141 0187 721750c0 bres 20672,#3
1143 018b 200e jra L105
1144 018d L305:
1145 ; 400 else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSE))
1147 018d 0d0a tnz (OFST+6,sp)
1148 018f 260a jrne L105
1150 0191 7b01 ld a,(OFST-3,sp)
1151 0193 a1b4 cp a,#180
1152 0195 2604 jrne L105
1153 ; 402 CLK->ECKR &= (u8)(~CLK_ECKR_HSEEN);
1155 0197 721150c1 bres 20673,#0
1156 019b L105:
1157 ; 405 return(Swif);
1159 019b 7b02 ld a,(OFST-2,sp)
1162 019d 5b06 addw sp,#6
1163 019f 81 ret
1301 ; 415 void CLK_HSIPrescalerConfig(CLK_Prescaler_TypeDef HSIPrescaler)
1301 ; 416 {
1302 switch .text
1303 01a0 _CLK_HSIPrescalerConfig:
1305 01a0 88 push a
1306 00000000 OFST: set 0
1309 ; 419 assert_param(IS_CLK_HSIPRESCALER_OK(HSIPrescaler));
1311 ; 422 CLK->CKDIVR &= (u8)(~CLK_CKDIVR_HSIDIV);
1313 01a1 c650c6 ld a,20678
1314 01a4 a4e7 and a,#231
1315 01a6 c750c6 ld 20678,a
1316 ; 425 CLK->CKDIVR |= (u8)HSIPrescaler;
1318 01a9 c650c6 ld a,20678
1319 01ac 1a01 or a,(OFST+1,sp)
1320 01ae c750c6 ld 20678,a
1321 ; 427 }
1324 01b1 84 pop a
1325 01b2 81 ret
1460 ; 438 void CLK_CCOConfig(CLK_Output_TypeDef CLK_CCO)
1460 ; 439 {
1461 switch .text
1462 01b3 _CLK_CCOConfig:
1464 01b3 88 push a
1465 00000000 OFST: set 0
1468 ; 442 assert_param(IS_CLK_OUTPUT_OK(CLK_CCO));
1470 ; 445 CLK->CCOR &= (u8)(~CLK_CCOR_CCOSEL);
1472 01b4 c650c9 ld a,20681
1473 01b7 a4e1 and a,#225
1474 01b9 c750c9 ld 20681,a
1475 ; 448 CLK->CCOR |= (u8)CLK_CCO;
1477 01bc c650c9 ld a,20681
1478 01bf 1a01 or a,(OFST+1,sp)
1479 01c1 c750c9 ld 20681,a
1480 ; 451 CLK->CCOR |= CLK_CCOR_CCOEN;
1482 01c4 721050c9 bset 20681,#0
1483 ; 453 }
1486 01c8 84 pop a
1487 01c9 81 ret
1552 ; 463 void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
1552 ; 464 {
1553 switch .text
1554 01ca _CLK_ITConfig:
1556 01ca 89 pushw x
1557 00000000 OFST: set 0
1560 ; 467 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1562 ; 468 assert_param(IS_CLK_IT_OK(CLK_IT));
1564 ; 470 if (NewState != DISABLE)
1566 01cb 9f ld a,xl
1567 01cc 4d tnz a
1568 01cd 2719 jreq L507
1569 ; 472 switch (CLK_IT)
1571 01cf 9e ld a,xh
1573 ; 480 default:
1573 ; 481 break;
1574 01d0 a00c sub a,#12
1575 01d2 270a jreq L146
1576 01d4 a010 sub a,#16
1577 01d6 2624 jrne L317
1578 ; 474 case CLK_IT_SWIF: /* Enable the clock switch interrupt */
1578 ; 475 CLK->SWCR |= CLK_SWCR_SWIEN;
1580 01d8 721450c5 bset 20677,#2
1581 ; 476 break;
1583 01dc 201e jra L317
1584 01de L146:
1585 ; 477 case CLK_IT_CSSD: /* Enable the clock security system detection interrupt */
1585 ; 478 CLK->CSSR |= CLK_CSSR_CSSDIE;
1587 01de 721450c8 bset 20680,#2
1588 ; 479 break;
1590 01e2 2018 jra L317
1591 01e4 L346:
1592 ; 480 default:
1592 ; 481 break;
1594 01e4 2016 jra L317
1595 01e6 L117:
1597 01e6 2014 jra L317
1598 01e8 L507:
1599 ; 486 switch (CLK_IT)
1601 01e8 7b01 ld a,(OFST+1,sp)
1603 ; 494 default:
1603 ; 495 break;
1604 01ea a00c sub a,#12
1605 01ec 270a jreq L746
1606 01ee a010 sub a,#16
1607 01f0 260a jrne L317
1608 ; 488 case CLK_IT_SWIF: /* Disable the clock switch interrupt */
1608 ; 489 CLK->SWCR &= (u8)(~CLK_SWCR_SWIEN);
1610 01f2 721550c5 bres 20677,#2
1611 ; 490 break;
1613 01f6 2004 jra L317
1614 01f8 L746:
1615 ; 491 case CLK_IT_CSSD: /* Disable the clock security system detection interrupt */
1615 ; 492 CLK->CSSR &= (u8)(~CLK_CSSR_CSSDIE);
1617 01f8 721550c8 bres 20680,#2
1618 ; 493 break;
1619 01fc L317:
1620 ; 499 }
1623 01fc 85 popw x
1624 01fd 81 ret
1625 01fe L156:
1626 ; 494 default:
1626 ; 495 break;
1628 01fe 20fc jra L317
1629 0200 L717:
1630 0200 20fa jra L317
1665 ; 506 void CLK_SYSCLKConfig(CLK_Prescaler_TypeDef ClockPrescaler)
1665 ; 507 {
1666 switch .text
1667 0202 _CLK_SYSCLKConfig:
1669 0202 88 push a
1670 00000000 OFST: set 0
1673 ; 510 assert_param(IS_CLK_PRESCALER_OK(ClockPrescaler));
1675 ; 512 if (((u8)ClockPrescaler & (u8)0x80) == 0x00) /* Bit7 = 0 means HSI divider */
1677 0203 a580 bcp a,#128
1678 0205 2614 jrne L737
1679 ; 514 CLK->CKDIVR &= (u8)(~CLK_CKDIVR_HSIDIV);
1681 0207 c650c6 ld a,20678
1682 020a a4e7 and a,#231
1683 020c c750c6 ld 20678,a
1684 ; 515 CLK->CKDIVR |= (u8)((u8)ClockPrescaler & (u8)CLK_CKDIVR_HSIDIV);
1686 020f 7b01 ld a,(OFST+1,sp)
1687 0211 a418 and a,#24
1688 0213 ca50c6 or a,20678
1689 0216 c750c6 ld 20678,a
1691 0219 2012 jra L147
1692 021b L737:
1693 ; 519 CLK->CKDIVR &= (u8)(~CLK_CKDIVR_CPUDIV);
1695 021b c650c6 ld a,20678
1696 021e a4f8 and a,#248
1697 0220 c750c6 ld 20678,a
1698 ; 520 CLK->CKDIVR |= (u8)((u8)ClockPrescaler & (u8)CLK_CKDIVR_CPUDIV);
1700 0223 7b01 ld a,(OFST+1,sp)
1701 0225 a407 and a,#7
1702 0227 ca50c6 or a,20678
1703 022a c750c6 ld 20678,a
1704 022d L147:
1705 ; 523 }
1708 022d 84 pop a
1709 022e 81 ret
1765 ; 530 void CLK_SWIMConfig(CLK_SWIMDivider_TypeDef CLK_SWIMDivider)
1765 ; 531 {
1766 switch .text
1767 022f _CLK_SWIMConfig:
1771 ; 534 assert_param(IS_CLK_SWIMDIVIDER_OK(CLK_SWIMDivider));
1773 ; 536 if (CLK_SWIMDivider != CLK_SWIMDIVIDER_2)
1775 022f 4d tnz a
1776 0230 2706 jreq L177
1777 ; 539 CLK->SWIMCCR |= CLK_SWIMCCR_SWIMDIV;
1779 0232 721050cd bset 20685,#0
1781 0236 2004 jra L377
1782 0238 L177:
1783 ; 544 CLK->SWIMCCR &= (u8)(~CLK_SWIMCCR_SWIMDIV);
1785 0238 721150cd bres 20685,#0
1786 023c L377:
1787 ; 547 }
1790 023c 81 ret
1887 ; 555 void CLK_CANConfig(CLK_CANDivider_TypeDef CLK_CANDivider)
1887 ; 556 {
1888 switch .text
1889 023d _CLK_CANConfig:
1891 023d 88 push a
1892 00000000 OFST: set 0
1895 ; 559 assert_param(IS_CLK_CANDIVIDER_OK(CLK_CANDivider));
1897 ; 562 CLK->CANCCR &= (u8)(~CLK_CANCCR_CANDIV);
1899 023e c650cb ld a,20683
1900 0241 a4f8 and a,#248
1901 0243 c750cb ld 20683,a
1902 ; 565 CLK->CANCCR |= (u8)CLK_CANDivider;
1904 0246 c650cb ld a,20683
1905 0249 1a01 or a,(OFST+1,sp)
1906 024b c750cb ld 20683,a
1907 ; 567 }
1910 024e 84 pop a
1911 024f 81 ret
1935 ; 577 void CLK_ClockSecuritySystemEnable(void)
1935 ; 578 {
1936 switch .text
1937 0250 _CLK_ClockSecuritySystemEnable:
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