📄 stm8s_tim2.ls
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3643 ; 1088 assert_param(IS_TIM2_GET_FLAG_OK(TIM2_FLAG));
3645 ; 1090 tim2_flag_l = (u8)(TIM2_FLAG);
3647 0419 9f ld a,xl
3648 041a 6b02 ld (OFST-2,sp),a
3649 ; 1091 tim2_flag_h = (u8)(TIM2_FLAG >> 8);
3651 041c 9e ld a,xh
3652 041d 6b03 ld (OFST-1,sp),a
3653 ; 1093 if (((TIM2->SR1 & tim2_flag_l) | (TIM2->SR2 & tim2_flag_h)) != (u8)RESET )
3655 041f c65303 ld a,21251
3656 0422 1403 and a,(OFST-1,sp)
3657 0424 6b01 ld (OFST-3,sp),a
3658 0426 c65302 ld a,21250
3659 0429 1402 and a,(OFST-2,sp)
3660 042b 1a01 or a,(OFST-3,sp)
3661 042d 2706 jreq L7271
3662 ; 1095 bitstatus = SET;
3664 042f a601 ld a,#1
3665 0431 6b04 ld (OFST+0,sp),a
3667 0433 2002 jra L1371
3668 0435 L7271:
3669 ; 1099 bitstatus = RESET;
3671 0435 0f04 clr (OFST+0,sp)
3672 0437 L1371:
3673 ; 1101 return (FlagStatus)bitstatus;
3675 0437 7b04 ld a,(OFST+0,sp)
3678 0439 5b04 addw sp,#4
3679 043b 81 ret
3714 ; 1118 void TIM2_ClearFlag(TIM2_FLAG_TypeDef TIM2_FLAG)
3714 ; 1119 {
3715 switch .text
3716 043c _TIM2_ClearFlag:
3718 043c 89 pushw x
3719 00000000 OFST: set 0
3722 ; 1121 assert_param(IS_TIM2_CLEAR_FLAG_OK(TIM2_FLAG));
3724 ; 1124 TIM2->SR1 = (u8)(~((u8)(TIM2_FLAG)));
3726 043d 9f ld a,xl
3727 043e 43 cpl a
3728 043f c75302 ld 21250,a
3729 ; 1125 TIM2->SR2 = (u8)(~((u8)(TIM2_FLAG >> 8)));
3731 0442 7b01 ld a,(OFST+1,sp)
3732 0444 43 cpl a
3733 0445 c75303 ld 21251,a
3734 ; 1126 }
3737 0448 85 popw x
3738 0449 81 ret
3802 ; 1140 ITStatus TIM2_GetITStatus(TIM2_IT_TypeDef TIM2_IT)
3802 ; 1141 {
3803 switch .text
3804 044a _TIM2_GetITStatus:
3806 044a 88 push a
3807 044b 5203 subw sp,#3
3808 00000003 OFST: set 3
3811 ; 1142 volatile ITStatus bitstatus = RESET;
3813 044d 0f03 clr (OFST+0,sp)
3814 ; 1143 vu8 TIM2_itStatus = 0, TIM2_itEnable = 0;
3816 044f 0f01 clr (OFST-2,sp)
3819 0451 0f02 clr (OFST-1,sp)
3820 ; 1146 assert_param(IS_TIM2_GET_IT_OK(TIM2_IT));
3822 ; 1148 TIM2_itStatus = (u8)(TIM2->SR1 & TIM2_IT);
3824 0453 c45302 and a,21250
3825 0456 6b01 ld (OFST-2,sp),a
3826 ; 1150 TIM2_itEnable = (u8)(TIM2->IER & TIM2_IT);
3828 0458 c65301 ld a,21249
3829 045b 1404 and a,(OFST+1,sp)
3830 045d 6b02 ld (OFST-1,sp),a
3831 ; 1152 if ((TIM2_itStatus != (u8)RESET ) && (TIM2_itEnable != (u8)RESET ))
3833 045f 0d01 tnz (OFST-2,sp)
3834 0461 270a jreq L3002
3836 0463 0d02 tnz (OFST-1,sp)
3837 0465 2706 jreq L3002
3838 ; 1154 bitstatus = SET;
3840 0467 a601 ld a,#1
3841 0469 6b03 ld (OFST+0,sp),a
3843 046b 2002 jra L5002
3844 046d L3002:
3845 ; 1158 bitstatus = RESET;
3847 046d 0f03 clr (OFST+0,sp)
3848 046f L5002:
3849 ; 1160 return (ITStatus)(bitstatus);
3851 046f 7b03 ld a,(OFST+0,sp)
3854 0471 5b04 addw sp,#4
3855 0473 81 ret
3891 ; 1174 void TIM2_ClearITPendingBit(TIM2_IT_TypeDef TIM2_IT)
3891 ; 1175 {
3892 switch .text
3893 0474 _TIM2_ClearITPendingBit:
3897 ; 1177 assert_param(IS_TIM2_IT_OK(TIM2_IT));
3899 ; 1180 TIM2->SR1 = (u8)(~TIM2_IT);
3901 0474 43 cpl a
3902 0475 c75302 ld 21250,a
3903 ; 1181 }
3906 0478 81 ret
3958 ; 1200 static void TI1_Config(u8 TIM2_ICPolarity,
3958 ; 1201 u8 TIM2_ICSelection,
3958 ; 1202 u8 TIM2_ICFilter)
3958 ; 1203 {
3959 switch .text
3960 0479 L3_TI1_Config:
3962 0479 89 pushw x
3963 047a 88 push a
3964 00000001 OFST: set 1
3967 ; 1205 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC1E);
3969 047b 72115308 bres 21256,#0
3970 ; 1208 TIM2->CCMR1 = (u8)((TIM2->CCMR1 & (u8)(~( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF ))) | (u8)(( (TIM2_ICSelection)) | ((u8)( TIM2_ICFilter << 4))));
3972 047f 7b06 ld a,(OFST+5,sp)
3973 0481 97 ld xl,a
3974 0482 a610 ld a,#16
3975 0484 42 mul x,a
3976 0485 9f ld a,xl
3977 0486 1a03 or a,(OFST+2,sp)
3978 0488 6b01 ld (OFST+0,sp),a
3979 048a c65305 ld a,21253
3980 048d a40c and a,#12
3981 048f 1a01 or a,(OFST+0,sp)
3982 0491 c75305 ld 21253,a
3983 ; 1211 if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)
3985 0494 0d02 tnz (OFST+1,sp)
3986 0496 2706 jreq L3502
3987 ; 1213 TIM2->CCER1 |= TIM2_CCER1_CC1P;
3989 0498 72125308 bset 21256,#1
3991 049c 2004 jra L5502
3992 049e L3502:
3993 ; 1217 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC1P);
3995 049e 72135308 bres 21256,#1
3996 04a2 L5502:
3997 ; 1220 TIM2->CCER1 |= TIM2_CCER1_CC1E;
3999 04a2 72105308 bset 21256,#0
4000 ; 1221 }
4003 04a6 5b03 addw sp,#3
4004 04a8 81 ret
4056 ; 1240 static void TI2_Config(u8 TIM2_ICPolarity,
4056 ; 1241 u8 TIM2_ICSelection,
4056 ; 1242 u8 TIM2_ICFilter)
4056 ; 1243 {
4057 switch .text
4058 04a9 L5_TI2_Config:
4060 04a9 89 pushw x
4061 04aa 88 push a
4062 00000001 OFST: set 1
4065 ; 1245 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC2E);
4067 04ab 72195308 bres 21256,#4
4068 ; 1248 TIM2->CCMR2 = (u8)((TIM2->CCMR2 & (u8)(~( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF ))) | (u8)(( (TIM2_ICSelection)) | ((u8)( TIM2_ICFilter << 4))));
4070 04af 7b06 ld a,(OFST+5,sp)
4071 04b1 97 ld xl,a
4072 04b2 a610 ld a,#16
4073 04b4 42 mul x,a
4074 04b5 9f ld a,xl
4075 04b6 1a03 or a,(OFST+2,sp)
4076 04b8 6b01 ld (OFST+0,sp),a
4077 04ba c65306 ld a,21254
4078 04bd a40c and a,#12
4079 04bf 1a01 or a,(OFST+0,sp)
4080 04c1 c75306 ld 21254,a
4081 ; 1252 if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)
4083 04c4 0d02 tnz (OFST+1,sp)
4084 04c6 2706 jreq L5012
4085 ; 1254 TIM2->CCER1 |= TIM2_CCER1_CC2P;
4087 04c8 721a5308 bset 21256,#5
4089 04cc 2004 jra L7012
4090 04ce L5012:
4091 ; 1258 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC2P);
4093 04ce 721b5308 bres 21256,#5
4094 04d2 L7012:
4095 ; 1262 TIM2->CCER1 |= TIM2_CCER1_CC2E;
4097 04d2 72185308 bset 21256,#4
4098 ; 1264 }
4101 04d6 5b03 addw sp,#3
4102 04d8 81 ret
4154 ; 1280 static void TI3_Config(u8 TIM2_ICPolarity, u8 TIM2_ICSelection,
4154 ; 1281 u8 TIM2_ICFilter)
4154 ; 1282 {
4155 switch .text
4156 04d9 L7_TI3_Config:
4158 04d9 89 pushw x
4159 04da 88 push a
4160 00000001 OFST: set 1
4163 ; 1284 TIM2->CCER2 &= (u8)(~TIM2_CCER2_CC3E);
4165 04db 72115309 bres 21257,#0
4166 ; 1287 TIM2->CCMR3 = (u8)((TIM2->CCMR3 & (u8)(~( TIM2_CCMR_CCxS | TIM2_CCMR_ICxF ))) | (u8)(( (TIM2_ICSelection)) | ((u8)( TIM2_ICFilter << 4))));
4168 04df 7b06 ld a,(OFST+5,sp)
4169 04e1 97 ld xl,a
4170 04e2 a610 ld a,#16
4171 04e4 42 mul x,a
4172 04e5 9f ld a,xl
4173 04e6 1a03 or a,(OFST+2,sp)
4174 04e8 6b01 ld (OFST+0,sp),a
4175 04ea c65307 ld a,21255
4176 04ed a40c and a,#12
4177 04ef 1a01 or a,(OFST+0,sp)
4178 04f1 c75307 ld 21255,a
4179 ; 1291 if (TIM2_ICPolarity != TIM2_ICPOLARITY_RISING)
4181 04f4 0d02 tnz (OFST+1,sp)
4182 04f6 2706 jreq L7312
4183 ; 1293 TIM2->CCER2 |= TIM2_CCER2_CC3P;
4185 04f8 72125309 bset 21257,#1
4187 04fc 2004 jra L1412
4188 04fe L7312:
4189 ; 1297 TIM2->CCER2 &= (u8)(~TIM2_CCER2_CC3P);
4191 04fe 72135309 bres 21257,#1
4192 0502 L1412:
4193 ; 1300 TIM2->CCER2 |= TIM2_CCER2_CC3E;
4195 0502 72105309 bset 21257,#0
4196 ; 1301 }
4199 0506 5b03 addw sp,#3
4200 0508 81 ret
4213 xdef _TIM2_ClearITPendingBit
4214 xdef _TIM2_GetITStatus
4215 xdef _TIM2_ClearFlag
4216 xdef _TIM2_GetFlagStatus
4217 xdef _TIM2_GetPrescaler
4218 xdef _TIM2_GetCounter
4219 xdef _TIM2_GetCapture3
4220 xdef _TIM2_GetCapture2
4221 xdef _TIM2_GetCapture1
4222 xdef _TIM2_SetIC3Prescaler
4223 xdef _TIM2_SetIC2Prescaler
4224 xdef _TIM2_SetIC1Prescaler
4225 xdef _TIM2_SetCompare3
4226 xdef _TIM2_SetCompare2
4227 xdef _TIM2_SetCompare1
4228 xdef _TIM2_SetAutoreload
4229 xdef _TIM2_SetCounter
4230 xdef _TIM2_SelectOCxM
4231 xdef _TIM2_CCxCmd
4232 xdef _TIM2_OC3PolarityConfig
4233 xdef _TIM2_OC2PolarityConfig
4234 xdef _TIM2_OC1PolarityConfig
4235 xdef _TIM2_GenerateEvent
4236 xdef _TIM2_OC3PreloadConfig
4237 xdef _TIM2_OC2PreloadConfig
4238 xdef _TIM2_OC1PreloadConfig
4239 xdef _TIM2_ARRPreloadConfig
4240 xdef _TIM2_ForcedOC3Config
4241 xdef _TIM2_ForcedOC2Config
4242 xdef _TIM2_ForcedOC1Config
4243 xdef _TIM2_PrescalerConfig
4244 xdef _TIM2_SelectOnePulseMode
4245 xdef _TIM2_UpdateRequestConfig
4246 xdef _TIM2_UpdateDisableConfig
4247 xdef _TIM2_ITConfig
4248 xdef _TIM2_Cmd
4249 xdef _TIM2_PWMIConfig
4250 xdef _TIM2_ICInit
4251 xdef _TIM2_OC3Init
4252 xdef _TIM2_OC2Init
4253 xdef _TIM2_OC1Init
4254 xdef _TIM2_TimeBaseInit
4255 xdef _TIM2_DeInit
4274 end
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