📄 stm8s_tim2.ls
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2721 ; 859 }
2724 0322 81 ret
2758 ; 868 void TIM2_SetAutoreload(u16 Autoreload)
2758 ; 869 {
2759 switch .text
2760 0323 _TIM2_SetAutoreload:
2764 ; 872 TIM2->ARRH = (u8)(Autoreload >> 8);
2766 0323 9e ld a,xh
2767 0324 c7530d ld 21261,a
2768 ; 873 TIM2->ARRL = (u8)(Autoreload);
2770 0327 9f ld a,xl
2771 0328 c7530e ld 21262,a
2772 ; 875 }
2775 032b 81 ret
2809 ; 884 void TIM2_SetCompare1(u16 Compare1)
2809 ; 885 {
2810 switch .text
2811 032c _TIM2_SetCompare1:
2815 ; 887 TIM2->CCR1H = (u8)(Compare1 >> 8);
2817 032c 9e ld a,xh
2818 032d c7530f ld 21263,a
2819 ; 888 TIM2->CCR1L = (u8)(Compare1);
2821 0330 9f ld a,xl
2822 0331 c75310 ld 21264,a
2823 ; 890 }
2826 0334 81 ret
2860 ; 899 void TIM2_SetCompare2(u16 Compare2)
2860 ; 900 {
2861 switch .text
2862 0335 _TIM2_SetCompare2:
2866 ; 902 TIM2->CCR2H = (u8)(Compare2 >> 8);
2868 0335 9e ld a,xh
2869 0336 c75311 ld 21265,a
2870 ; 903 TIM2->CCR2L = (u8)(Compare2);
2872 0339 9f ld a,xl
2873 033a c75312 ld 21266,a
2874 ; 905 }
2877 033d 81 ret
2911 ; 914 void TIM2_SetCompare3(u16 Compare3)
2911 ; 915 {
2912 switch .text
2913 033e _TIM2_SetCompare3:
2917 ; 917 TIM2->CCR3H = (u8)(Compare3 >> 8);
2919 033e 9e ld a,xh
2920 033f c75313 ld 21267,a
2921 ; 918 TIM2->CCR3L = (u8)(Compare3);
2923 0342 9f ld a,xl
2924 0343 c75314 ld 21268,a
2925 ; 920 }
2928 0346 81 ret
2964 ; 933 void TIM2_SetIC1Prescaler(TIM2_ICPSC_TypeDef TIM2_IC1Prescaler)
2964 ; 934 {
2965 switch .text
2966 0347 _TIM2_SetIC1Prescaler:
2968 0347 88 push a
2969 00000000 OFST: set 0
2972 ; 936 assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_IC1Prescaler));
2974 ; 939 TIM2->CCMR1 = (u8)((TIM2->CCMR1 & (u8)(~TIM2_CCMR_ICxPSC)) | (u8)TIM2_IC1Prescaler);
2976 0348 c65305 ld a,21253
2977 034b a4f3 and a,#243
2978 034d 1a01 or a,(OFST+1,sp)
2979 034f c75305 ld 21253,a
2980 ; 940 }
2983 0352 84 pop a
2984 0353 81 ret
3020 ; 952 void TIM2_SetIC2Prescaler(TIM2_ICPSC_TypeDef TIM2_IC2Prescaler)
3020 ; 953 {
3021 switch .text
3022 0354 _TIM2_SetIC2Prescaler:
3024 0354 88 push a
3025 00000000 OFST: set 0
3028 ; 955 assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_IC2Prescaler));
3030 ; 958 TIM2->CCMR2 = (u8)((TIM2->CCMR2 & (u8)(~TIM2_CCMR_ICxPSC)) | (u8)TIM2_IC2Prescaler);
3032 0355 c65306 ld a,21254
3033 0358 a4f3 and a,#243
3034 035a 1a01 or a,(OFST+1,sp)
3035 035c c75306 ld 21254,a
3036 ; 959 }
3039 035f 84 pop a
3040 0360 81 ret
3076 ; 971 void TIM2_SetIC3Prescaler(TIM2_ICPSC_TypeDef TIM2_IC3Prescaler)
3076 ; 972 {
3077 switch .text
3078 0361 _TIM2_SetIC3Prescaler:
3080 0361 88 push a
3081 00000000 OFST: set 0
3084 ; 975 assert_param(IS_TIM2_IC_PRESCALER_OK(TIM2_IC3Prescaler));
3086 ; 977 TIM2->CCMR3 = (u8)((TIM2->CCMR3 & (u8)(~TIM2_CCMR_ICxPSC)) | (u8)TIM2_IC3Prescaler);
3088 0362 c65307 ld a,21255
3089 0365 a4f3 and a,#243
3090 0367 1a01 or a,(OFST+1,sp)
3091 0369 c75307 ld 21255,a
3092 ; 978 }
3095 036c 84 pop a
3096 036d 81 ret
3148 ; 986 u16 TIM2_GetCapture1(void)
3148 ; 987 {
3149 switch .text
3150 036e _TIM2_GetCapture1:
3152 036e 5204 subw sp,#4
3153 00000004 OFST: set 4
3156 ; 989 u16 tmpccr1 = 0;
3158 0370 1e03 ldw x,(OFST-1,sp)
3159 ; 990 u8 tmpccr1l=0, tmpccr1h=0;
3161 0372 7b01 ld a,(OFST-3,sp)
3162 0374 97 ld xl,a
3165 0375 7b02 ld a,(OFST-2,sp)
3166 0377 97 ld xl,a
3167 ; 992 tmpccr1h = TIM2->CCR1H;
3169 0378 c6530f ld a,21263
3170 037b 6b02 ld (OFST-2,sp),a
3171 ; 993 tmpccr1l = TIM2->CCR1L;
3173 037d c65310 ld a,21264
3174 0380 6b01 ld (OFST-3,sp),a
3175 ; 995 tmpccr1 = (u16)(tmpccr1l);
3177 0382 7b01 ld a,(OFST-3,sp)
3178 0384 5f clrw x
3179 0385 97 ld xl,a
3180 0386 1f03 ldw (OFST-1,sp),x
3181 ; 996 tmpccr1 |= (u16)((u16)tmpccr1h << 8);
3183 0388 7b02 ld a,(OFST-2,sp)
3184 038a 5f clrw x
3185 038b 97 ld xl,a
3186 038c 4f clr a
3187 038d 02 rlwa x,a
3188 038e 01 rrwa x,a
3189 038f 1a04 or a,(OFST+0,sp)
3190 0391 01 rrwa x,a
3191 0392 1a03 or a,(OFST-1,sp)
3192 0394 01 rrwa x,a
3193 0395 1f03 ldw (OFST-1,sp),x
3194 ; 998 return (u16)tmpccr1;
3196 0397 1e03 ldw x,(OFST-1,sp)
3199 0399 5b04 addw sp,#4
3200 039b 81 ret
3252 ; 1007 u16 TIM2_GetCapture2(void)
3252 ; 1008 {
3253 switch .text
3254 039c _TIM2_GetCapture2:
3256 039c 5204 subw sp,#4
3257 00000004 OFST: set 4
3260 ; 1010 u16 tmpccr2 = 0;
3262 039e 1e03 ldw x,(OFST-1,sp)
3263 ; 1011 u8 tmpccr2l=0, tmpccr2h=0;
3265 03a0 7b01 ld a,(OFST-3,sp)
3266 03a2 97 ld xl,a
3269 03a3 7b02 ld a,(OFST-2,sp)
3270 03a5 97 ld xl,a
3271 ; 1013 tmpccr2h = TIM2->CCR2H;
3273 03a6 c65311 ld a,21265
3274 03a9 6b02 ld (OFST-2,sp),a
3275 ; 1014 tmpccr2l = TIM2->CCR2L;
3277 03ab c65312 ld a,21266
3278 03ae 6b01 ld (OFST-3,sp),a
3279 ; 1016 tmpccr2 = (u16)(tmpccr2l);
3281 03b0 7b01 ld a,(OFST-3,sp)
3282 03b2 5f clrw x
3283 03b3 97 ld xl,a
3284 03b4 1f03 ldw (OFST-1,sp),x
3285 ; 1017 tmpccr2 |= (u16)((u16)tmpccr2h << 8);
3287 03b6 7b02 ld a,(OFST-2,sp)
3288 03b8 5f clrw x
3289 03b9 97 ld xl,a
3290 03ba 4f clr a
3291 03bb 02 rlwa x,a
3292 03bc 01 rrwa x,a
3293 03bd 1a04 or a,(OFST+0,sp)
3294 03bf 01 rrwa x,a
3295 03c0 1a03 or a,(OFST-1,sp)
3296 03c2 01 rrwa x,a
3297 03c3 1f03 ldw (OFST-1,sp),x
3298 ; 1019 return (u16)tmpccr2;
3300 03c5 1e03 ldw x,(OFST-1,sp)
3303 03c7 5b04 addw sp,#4
3304 03c9 81 ret
3356 ; 1028 u16 TIM2_GetCapture3(void)
3356 ; 1029 {
3357 switch .text
3358 03ca _TIM2_GetCapture3:
3360 03ca 5204 subw sp,#4
3361 00000004 OFST: set 4
3364 ; 1031 u16 tmpccr3 = 0;
3366 03cc 1e03 ldw x,(OFST-1,sp)
3367 ; 1032 u8 tmpccr3l=0, tmpccr3h=0;
3369 03ce 7b01 ld a,(OFST-3,sp)
3370 03d0 97 ld xl,a
3373 03d1 7b02 ld a,(OFST-2,sp)
3374 03d3 97 ld xl,a
3375 ; 1034 tmpccr3h = TIM2->CCR3H;
3377 03d4 c65313 ld a,21267
3378 03d7 6b02 ld (OFST-2,sp),a
3379 ; 1035 tmpccr3l = TIM2->CCR3L;
3381 03d9 c65314 ld a,21268
3382 03dc 6b01 ld (OFST-3,sp),a
3383 ; 1037 tmpccr3 = (u16)(tmpccr3l);
3385 03de 7b01 ld a,(OFST-3,sp)
3386 03e0 5f clrw x
3387 03e1 97 ld xl,a
3388 03e2 1f03 ldw (OFST-1,sp),x
3389 ; 1038 tmpccr3 |= (u16)((u16)tmpccr3h << 8);
3391 03e4 7b02 ld a,(OFST-2,sp)
3392 03e6 5f clrw x
3393 03e7 97 ld xl,a
3394 03e8 4f clr a
3395 03e9 02 rlwa x,a
3396 03ea 01 rrwa x,a
3397 03eb 1a04 or a,(OFST+0,sp)
3398 03ed 01 rrwa x,a
3399 03ee 1a03 or a,(OFST-1,sp)
3400 03f0 01 rrwa x,a
3401 03f1 1f03 ldw (OFST-1,sp),x
3402 ; 1040 return (u16)tmpccr3;
3404 03f3 1e03 ldw x,(OFST-1,sp)
3407 03f5 5b04 addw sp,#4
3408 03f7 81 ret
3431 ; 1049 u16 TIM2_GetCounter(void)
3431 ; 1050 {
3432 switch .text
3433 03f8 _TIM2_GetCounter:
3435 03f8 89 pushw x
3436 00000002 OFST: set 2
3439 ; 1052 return (u16)(((u16)TIM2->CNTRH << 8) | (u16)(TIM2->CNTRL));
3441 03f9 c6530b ld a,21259
3442 03fc 5f clrw x
3443 03fd 97 ld xl,a
3444 03fe 1f01 ldw (OFST-1,sp),x
3445 0400 c6530a ld a,21258
3446 0403 5f clrw x
3447 0404 97 ld xl,a
3448 0405 4f clr a
3449 0406 02 rlwa x,a
3450 0407 01 rrwa x,a
3451 0408 1a02 or a,(OFST+0,sp)
3452 040a 01 rrwa x,a
3453 040b 1a01 or a,(OFST-1,sp)
3454 040d 01 rrwa x,a
3457 040e 5b02 addw sp,#2
3458 0410 81 ret
3482 ; 1062 TIM2_Prescaler_TypeDef TIM2_GetPrescaler(void)
3482 ; 1063 {
3483 switch .text
3484 0411 _TIM2_GetPrescaler:
3488 ; 1065 return (TIM2_Prescaler_TypeDef)(TIM2->PSCR);
3490 0411 c6530c ld a,21260
3493 0414 81 ret
3632 ; 1082 FlagStatus TIM2_GetFlagStatus(TIM2_FLAG_TypeDef TIM2_FLAG)
3632 ; 1083 {
3633 switch .text
3634 0415 _TIM2_GetFlagStatus:
3636 0415 5204 subw sp,#4
3637 00000004 OFST: set 4
3640 ; 1084 volatile FlagStatus bitstatus = RESET;
3642 0417 0f04 clr (OFST+0,sp)
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