📄 stm8s_tim2.ls
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1878 ; 530 }
1881 022f 84 pop a
1882 0230 81 ret
1918 ; 541 void TIM2_ForcedOC3Config(TIM2_ForcedAction_TypeDef TIM2_ForcedAction)
1918 ; 542 {
1919 switch .text
1920 0231 _TIM2_ForcedOC3Config:
1922 0231 88 push a
1923 00000000 OFST: set 0
1926 ; 544 assert_param(IS_TIM2_FORCED_ACTION_OK(TIM2_ForcedAction));
1928 ; 547 TIM2->CCMR3 = (u8)((TIM2->CCMR3 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_ForcedAction);
1930 0232 c65307 ld a,21255
1931 0235 a48f and a,#143
1932 0237 1a01 or a,(OFST+1,sp)
1933 0239 c75307 ld 21255,a
1934 ; 548 }
1937 023c 84 pop a
1938 023d 81 ret
1974 ; 557 void TIM2_ARRPreloadConfig(FunctionalState NewState)
1974 ; 558 {
1975 switch .text
1976 023e _TIM2_ARRPreloadConfig:
1980 ; 560 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1982 ; 563 if (NewState != DISABLE)
1984 023e 4d tnz a
1985 023f 2706 jreq L7201
1986 ; 565 TIM2->CR1 |= (u8)TIM2_CR1_ARPE;
1988 0241 721e5300 bset 21248,#7
1990 0245 2004 jra L1301
1991 0247 L7201:
1992 ; 569 TIM2->CR1 &= (u8)(~TIM2_CR1_ARPE);
1994 0247 721f5300 bres 21248,#7
1995 024b L1301:
1996 ; 571 }
1999 024b 81 ret
2035 ; 580 void TIM2_OC1PreloadConfig(FunctionalState NewState)
2035 ; 581 {
2036 switch .text
2037 024c _TIM2_OC1PreloadConfig:
2041 ; 583 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2043 ; 586 if (NewState != DISABLE)
2045 024c 4d tnz a
2046 024d 2706 jreq L1501
2047 ; 588 TIM2->CCMR1 |= (u8)TIM2_CCMR_OCxPE;
2049 024f 72165305 bset 21253,#3
2051 0253 2004 jra L3501
2052 0255 L1501:
2053 ; 592 TIM2->CCMR1 &= (u8)(~TIM2_CCMR_OCxPE);
2055 0255 72175305 bres 21253,#3
2056 0259 L3501:
2057 ; 594 }
2060 0259 81 ret
2096 ; 603 void TIM2_OC2PreloadConfig(FunctionalState NewState)
2096 ; 604 {
2097 switch .text
2098 025a _TIM2_OC2PreloadConfig:
2102 ; 606 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2104 ; 609 if (NewState != DISABLE)
2106 025a 4d tnz a
2107 025b 2706 jreq L3701
2108 ; 611 TIM2->CCMR2 |= (u8)TIM2_CCMR_OCxPE;
2110 025d 72165306 bset 21254,#3
2112 0261 2004 jra L5701
2113 0263 L3701:
2114 ; 615 TIM2->CCMR2 &= (u8)(~TIM2_CCMR_OCxPE);
2116 0263 72175306 bres 21254,#3
2117 0267 L5701:
2118 ; 617 }
2121 0267 81 ret
2157 ; 626 void TIM2_OC3PreloadConfig(FunctionalState NewState)
2157 ; 627 {
2158 switch .text
2159 0268 _TIM2_OC3PreloadConfig:
2163 ; 629 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2165 ; 632 if (NewState != DISABLE)
2167 0268 4d tnz a
2168 0269 2706 jreq L5111
2169 ; 634 TIM2->CCMR3 |= (u8)TIM2_CCMR_OCxPE;
2171 026b 72165307 bset 21255,#3
2173 026f 2004 jra L7111
2174 0271 L5111:
2175 ; 638 TIM2->CCMR3 &= (u8)(~TIM2_CCMR_OCxPE);
2177 0271 72175307 bres 21255,#3
2178 0275 L7111:
2179 ; 640 }
2182 0275 81 ret
2255 ; 653 void TIM2_GenerateEvent(TIM2_EventSource_TypeDef TIM2_EventSource)
2255 ; 654 {
2256 switch .text
2257 0276 _TIM2_GenerateEvent:
2261 ; 656 assert_param(IS_TIM2_EVENT_SOURCE_OK(TIM2_EventSource));
2263 ; 659 TIM2->EGR = (u8)TIM2_EventSource;
2265 0276 c75304 ld 21252,a
2266 ; 660 }
2269 0279 81 ret
2305 ; 671 void TIM2_OC1PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
2305 ; 672 {
2306 switch .text
2307 027a _TIM2_OC1PolarityConfig:
2311 ; 674 assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
2313 ; 677 if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)
2315 027a 4d tnz a
2316 027b 2706 jreq L1711
2317 ; 679 TIM2->CCER1 |= (u8)TIM2_CCER1_CC1P;
2319 027d 72125308 bset 21256,#1
2321 0281 2004 jra L3711
2322 0283 L1711:
2323 ; 683 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC1P);
2325 0283 72135308 bres 21256,#1
2326 0287 L3711:
2327 ; 685 }
2330 0287 81 ret
2366 ; 696 void TIM2_OC2PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
2366 ; 697 {
2367 switch .text
2368 0288 _TIM2_OC2PolarityConfig:
2372 ; 699 assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
2374 ; 702 if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)
2376 0288 4d tnz a
2377 0289 2706 jreq L3121
2378 ; 704 TIM2->CCER1 |= TIM2_CCER1_CC2P;
2380 028b 721a5308 bset 21256,#5
2382 028f 2004 jra L5121
2383 0291 L3121:
2384 ; 708 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC2P);
2386 0291 721b5308 bres 21256,#5
2387 0295 L5121:
2388 ; 710 }
2391 0295 81 ret
2427 ; 721 void TIM2_OC3PolarityConfig(TIM2_OCPolarity_TypeDef TIM2_OCPolarity)
2427 ; 722 {
2428 switch .text
2429 0296 _TIM2_OC3PolarityConfig:
2433 ; 724 assert_param(IS_TIM2_OC_POLARITY_OK(TIM2_OCPolarity));
2435 ; 727 if (TIM2_OCPolarity != TIM2_OCPOLARITY_HIGH)
2437 0296 4d tnz a
2438 0297 2706 jreq L5321
2439 ; 729 TIM2->CCER2 |= (u8)TIM2_CCER2_CC3P;
2441 0299 72125309 bset 21257,#1
2443 029d 2004 jra L7321
2444 029f L5321:
2445 ; 733 TIM2->CCER2 &= (u8)(~TIM2_CCER2_CC3P);
2447 029f 72135309 bres 21257,#1
2448 02a3 L7321:
2449 ; 735 }
2452 02a3 81 ret
2497 ; 749 void TIM2_CCxCmd(TIM2_Channel_TypeDef TIM2_Channel, FunctionalState NewState)
2497 ; 750 {
2498 switch .text
2499 02a4 _TIM2_CCxCmd:
2501 02a4 89 pushw x
2502 00000000 OFST: set 0
2505 ; 752 assert_param(IS_TIM2_CHANNEL_OK(TIM2_Channel));
2507 ; 753 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2509 ; 755 if (TIM2_Channel == TIM2_CHANNEL_1)
2511 02a5 9e ld a,xh
2512 02a6 4d tnz a
2513 02a7 2610 jrne L3621
2514 ; 758 if (NewState != DISABLE)
2516 02a9 9f ld a,xl
2517 02aa 4d tnz a
2518 02ab 2706 jreq L5621
2519 ; 760 TIM2->CCER1 |= (u8)TIM2_CCER1_CC1E;
2521 02ad 72105308 bset 21256,#0
2523 02b1 202a jra L1721
2524 02b3 L5621:
2525 ; 764 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC1E);
2527 02b3 72115308 bres 21256,#0
2528 02b7 2024 jra L1721
2529 02b9 L3621:
2530 ; 768 else if (TIM2_Channel == TIM2_CHANNEL_2)
2532 02b9 7b01 ld a,(OFST+1,sp)
2533 02bb a101 cp a,#1
2534 02bd 2610 jrne L3721
2535 ; 771 if (NewState != DISABLE)
2537 02bf 0d02 tnz (OFST+2,sp)
2538 02c1 2706 jreq L5721
2539 ; 773 TIM2->CCER1 |= (u8)TIM2_CCER1_CC2E;
2541 02c3 72185308 bset 21256,#4
2543 02c7 2014 jra L1721
2544 02c9 L5721:
2545 ; 777 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC2E);
2547 02c9 72195308 bres 21256,#4
2548 02cd 200e jra L1721
2549 02cf L3721:
2550 ; 783 if (NewState != DISABLE)
2552 02cf 0d02 tnz (OFST+2,sp)
2553 02d1 2706 jreq L3031
2554 ; 785 TIM2->CCER2 |= (u8)TIM2_CCER2_CC3E;
2556 02d3 72105309 bset 21257,#0
2558 02d7 2004 jra L1721
2559 02d9 L3031:
2560 ; 789 TIM2->CCER2 &= (u8)(~TIM2_CCER2_CC3E);
2562 02d9 72115309 bres 21257,#0
2563 02dd L1721:
2564 ; 792 }
2567 02dd 85 popw x
2568 02de 81 ret
2613 ; 814 void TIM2_SelectOCxM(TIM2_Channel_TypeDef TIM2_Channel, TIM2_OCMode_TypeDef TIM2_OCMode)
2613 ; 815 {
2614 switch .text
2615 02df _TIM2_SelectOCxM:
2617 02df 89 pushw x
2618 00000000 OFST: set 0
2621 ; 817 assert_param(IS_TIM2_CHANNEL_OK(TIM2_Channel));
2623 ; 818 assert_param(IS_TIM2_OCM_OK(TIM2_OCMode));
2625 ; 820 if (TIM2_Channel == TIM2_CHANNEL_1)
2627 02e0 9e ld a,xh
2628 02e1 4d tnz a
2629 02e2 2610 jrne L1331
2630 ; 823 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC1E);
2632 02e4 72115308 bres 21256,#0
2633 ; 826 TIM2->CCMR1 = (u8)((TIM2->CCMR1 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_OCMode);
2635 02e8 c65305 ld a,21253
2636 02eb a48f and a,#143
2637 02ed 1a02 or a,(OFST+2,sp)
2638 02ef c75305 ld 21253,a
2640 02f2 2024 jra L3331
2641 02f4 L1331:
2642 ; 828 else if (TIM2_Channel == TIM2_CHANNEL_2)
2644 02f4 7b01 ld a,(OFST+1,sp)
2645 02f6 a101 cp a,#1
2646 02f8 2610 jrne L5331
2647 ; 831 TIM2->CCER1 &= (u8)(~TIM2_CCER1_CC2E);
2649 02fa 72195308 bres 21256,#4
2650 ; 834 TIM2->CCMR2 = (u8)((TIM2->CCMR2 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_OCMode);
2652 02fe c65306 ld a,21254
2653 0301 a48f and a,#143
2654 0303 1a02 or a,(OFST+2,sp)
2655 0305 c75306 ld 21254,a
2657 0308 200e jra L3331
2658 030a L5331:
2659 ; 839 TIM2->CCER2 &= (u8)(~TIM2_CCER2_CC3E);
2661 030a 72115309 bres 21257,#0
2662 ; 842 TIM2->CCMR3 = (u8)((TIM2->CCMR3 & (u8)(~TIM2_CCMR_OCM)) | (u8)TIM2_OCMode);
2664 030e c65307 ld a,21255
2665 0311 a48f and a,#143
2666 0313 1a02 or a,(OFST+2,sp)
2667 0315 c75307 ld 21255,a
2668 0318 L3331:
2669 ; 844 }
2672 0318 85 popw x
2673 0319 81 ret
2707 ; 853 void TIM2_SetCounter(u16 Counter)
2707 ; 854 {
2708 switch .text
2709 031a _TIM2_SetCounter:
2713 ; 856 TIM2->CNTRH = (u8)(Counter >> 8);
2715 031a 9e ld a,xh
2716 031b c7530a ld 21258,a
2717 ; 857 TIM2->CNTRL = (u8)(Counter);
2719 031e 9f ld a,xl
2720 031f c7530b ld 21259,a
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