📄 stm8s_clk.ls
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2038 switch .text
2039 025c _CLK_GetClockFreq:
2041 025c 5209 subw sp,#9
2042 00000009 OFST: set 9
2045 ; 606 u32 clockfrequency = 0;
2047 025e 96 ldw x,sp
2048 025f 1c0005 addw x,#OFST-4
2049 0262 cd0000 call c_ltor
2051 ; 607 CLK_Source_TypeDef clocksource = CLK_SOURCE_HSI;
2053 0265 7b09 ld a,(OFST+0,sp)
2054 0267 97 ld xl,a
2055 ; 608 u8 tmp = 0, presc = 0;
2057 0268 7b09 ld a,(OFST+0,sp)
2058 026a 97 ld xl,a
2061 026b 7b09 ld a,(OFST+0,sp)
2062 026d 97 ld xl,a
2063 ; 611 clocksource = (CLK_Source_TypeDef)CLK->CMSR;
2065 026e c650c3 ld a,20675
2066 0271 6b09 ld (OFST+0,sp),a
2067 ; 613 if (clocksource == CLK_SOURCE_HSI)
2069 0273 7b09 ld a,(OFST+0,sp)
2070 0275 a1e1 cp a,#225
2071 0277 2642 jrne L1111
2072 ; 615 tmp = (u8)(CLK->CKDIVR & CLK_CKDIVR_HSIDIV);
2074 0279 c650c6 ld a,20678
2075 027c a418 and a,#24
2076 027e 6b09 ld (OFST+0,sp),a
2077 ; 616 tmp = (u8)(tmp >> 3);
2079 0280 7b09 ld a,(OFST+0,sp)
2080 0282 44 srl a
2081 0283 44 srl a
2082 0284 44 srl a
2083 0285 6b09 ld (OFST+0,sp),a
2084 ; 617 presc = HSIDivFactor[tmp];
2086 0287 7b09 ld a,(OFST+0,sp)
2087 0289 5f clrw x
2088 028a 97 ld xl,a
2089 028b d60000 ld a,(_HSIDivFactor,x)
2090 028e 6b09 ld (OFST+0,sp),a
2091 ; 618 clockfrequency = HSI_VALUE / presc;
2093 0290 7b09 ld a,(OFST+0,sp)
2094 0292 b703 ld c_lreg+3,a
2095 0294 3f02 clr c_lreg+2
2096 0296 3f01 clr c_lreg+1
2097 0298 3f00 clr c_lreg
2098 029a 96 ldw x,sp
2099 029b 1c0001 addw x,#OFST-8
2100 029e cd0000 call c_rtol
2102 02a1 ae2400 ldw x,#9216
2103 02a4 bf02 ldw c_lreg+2,x
2104 02a6 ae00f4 ldw x,#244
2105 02a9 bf00 ldw c_lreg,x
2106 02ab 96 ldw x,sp
2107 02ac 1c0001 addw x,#OFST-8
2108 02af cd0000 call c_ludv
2110 02b2 96 ldw x,sp
2111 02b3 1c0005 addw x,#OFST-4
2112 02b6 cd0000 call c_rtol
2115 02b9 201c jra L3111
2116 02bb L1111:
2117 ; 620 else if ( clocksource == CLK_SOURCE_LSI)
2119 02bb 7b09 ld a,(OFST+0,sp)
2120 02bd a1d2 cp a,#210
2121 02bf 260c jrne L5111
2122 ; 622 clockfrequency = LSI_VALUE;
2124 02c1 aef400 ldw x,#62464
2125 02c4 1f07 ldw (OFST-2,sp),x
2126 02c6 ae0001 ldw x,#1
2127 02c9 1f05 ldw (OFST-4,sp),x
2129 02cb 200a jra L3111
2130 02cd L5111:
2131 ; 627 clockfrequency = 16000000;
2133 02cd ae2400 ldw x,#9216
2134 02d0 1f07 ldw (OFST-2,sp),x
2135 02d2 ae00f4 ldw x,#244
2136 02d5 1f05 ldw (OFST-4,sp),x
2137 02d7 L3111:
2138 ; 630 return((u32)clockfrequency);
2140 02d7 96 ldw x,sp
2141 02d8 1c0005 addw x,#OFST-4
2142 02db cd0000 call c_ltor
2146 02de 5b09 addw sp,#9
2147 02e0 81 ret
2246 ; 641 void CLK_AdjustHSICalibrationValue(CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)
2246 ; 642 {
2247 switch .text
2248 02e1 _CLK_AdjustHSICalibrationValue:
2250 02e1 88 push a
2251 00000000 OFST: set 0
2254 ; 645 assert_param(IS_CLK_HSITRIMVALUE_OK(CLK_HSICalibrationValue));
2256 ; 648 CLK->HSITRIMR = (u8)((CLK->HSITRIMR & (u8)(~CLK_HSITRIMR_HSITRIM))|((u8)CLK_HSICalibrationValue));
2258 02e2 c650cc ld a,20684
2259 02e5 a4f8 and a,#248
2260 02e7 1a01 or a,(OFST+1,sp)
2261 02e9 c750cc ld 20684,a
2262 ; 650 }
2265 02ec 84 pop a
2266 02ed 81 ret
2290 ; 662 void CLK_SYSCLKEmergencyClear(void)
2290 ; 663 {
2291 switch .text
2292 02ee _CLK_SYSCLKEmergencyClear:
2296 ; 664 CLK->SWCR &= (u8)(~CLK_SWCR_SWBSY);
2298 02ee 721150c5 bres 20677,#0
2299 ; 665 }
2302 02f2 81 ret
2455 ; 674 FlagStatus CLK_GetFlagStatus(CLK_Flag_TypeDef CLK_FLAG)
2455 ; 675 {
2456 switch .text
2457 02f3 _CLK_GetFlagStatus:
2459 02f3 89 pushw x
2460 02f4 5203 subw sp,#3
2461 00000003 OFST: set 3
2464 ; 677 u16 statusreg = 0;
2466 02f6 1e01 ldw x,(OFST-2,sp)
2467 ; 678 u8 tmpreg = 0;
2469 02f8 7b03 ld a,(OFST+0,sp)
2470 02fa 97 ld xl,a
2471 ; 679 FlagStatus bitstatus = RESET;
2473 02fb 7b03 ld a,(OFST+0,sp)
2474 02fd 97 ld xl,a
2475 ; 682 assert_param(IS_CLK_FLAG_OK(CLK_FLAG));
2477 ; 685 statusreg = (u16)((u16)CLK_FLAG & (u16)0xFF00);
2479 02fe 7b04 ld a,(OFST+1,sp)
2480 0300 97 ld xl,a
2481 0301 7b05 ld a,(OFST+2,sp)
2482 0303 9f ld a,xl
2483 0304 a4ff and a,#255
2484 0306 97 ld xl,a
2485 0307 4f clr a
2486 0308 02 rlwa x,a
2487 0309 1f01 ldw (OFST-2,sp),x
2488 030b 01 rrwa x,a
2489 ; 688 if (statusreg == 0x0100) /* The flag to check is in ICKRregister */
2491 030c 1e01 ldw x,(OFST-2,sp)
2492 030e a30100 cpw x,#256
2493 0311 2607 jrne L3621
2494 ; 690 tmpreg = CLK->ICKR;
2496 0313 c650c0 ld a,20672
2497 0316 6b03 ld (OFST+0,sp),a
2499 0318 202f jra L5621
2500 031a L3621:
2501 ; 692 else if (statusreg == 0x0200) /* The flag to check is in ECKRregister */
2503 031a 1e01 ldw x,(OFST-2,sp)
2504 031c a30200 cpw x,#512
2505 031f 2607 jrne L7621
2506 ; 694 tmpreg = CLK->ECKR;
2508 0321 c650c1 ld a,20673
2509 0324 6b03 ld (OFST+0,sp),a
2511 0326 2021 jra L5621
2512 0328 L7621:
2513 ; 696 else if (statusreg == 0x0300) /* The flag to check is in SWIC register */
2515 0328 1e01 ldw x,(OFST-2,sp)
2516 032a a30300 cpw x,#768
2517 032d 2607 jrne L3721
2518 ; 698 tmpreg = CLK->SWCR;
2520 032f c650c5 ld a,20677
2521 0332 6b03 ld (OFST+0,sp),a
2523 0334 2013 jra L5621
2524 0336 L3721:
2525 ; 700 else if (statusreg == 0x0400) /* The flag to check is in CSS register */
2527 0336 1e01 ldw x,(OFST-2,sp)
2528 0338 a30400 cpw x,#1024
2529 033b 2607 jrne L7721
2530 ; 702 tmpreg = CLK->CSSR;
2532 033d c650c8 ld a,20680
2533 0340 6b03 ld (OFST+0,sp),a
2535 0342 2005 jra L5621
2536 0344 L7721:
2537 ; 706 tmpreg = CLK->CCOR;
2539 0344 c650c9 ld a,20681
2540 0347 6b03 ld (OFST+0,sp),a
2541 0349 L5621:
2542 ; 709 if ((tmpreg & (u8)CLK_FLAG) != (u8)RESET)
2544 0349 7b05 ld a,(OFST+2,sp)
2545 034b 1503 bcp a,(OFST+0,sp)
2546 034d 2706 jreq L3031
2547 ; 711 bitstatus = SET;
2549 034f a601 ld a,#1
2550 0351 6b03 ld (OFST+0,sp),a
2552 0353 2002 jra L5031
2553 0355 L3031:
2554 ; 715 bitstatus = RESET;
2556 0355 0f03 clr (OFST+0,sp)
2557 0357 L5031:
2558 ; 719 return((FlagStatus)bitstatus);
2560 0357 7b03 ld a,(OFST+0,sp)
2563 0359 5b05 addw sp,#5
2564 035b 81 ret
2610 ; 729 ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT)
2610 ; 730 {
2611 switch .text
2612 035c _CLK_GetITStatus:
2614 035c 88 push a
2615 035d 88 push a
2616 00000001 OFST: set 1
2619 ; 732 ITStatus bitstatus = RESET;
2621 035e 0f01 clr (OFST+0,sp)
2622 ; 735 assert_param(IS_CLK_IT_OK(CLK_IT));
2624 ; 737 if (CLK_IT == CLK_IT_SWIF)
2626 0360 a11c cp a,#28
2627 0362 2611 jrne L1331
2628 ; 740 if ((CLK->SWCR & (u8)CLK_IT) == (u8)0x0C)
2630 0364 c450c5 and a,20677
2631 0367 a10c cp a,#12
2632 0369 2606 jrne L3331
2633 ; 742 bitstatus = SET;
2635 036b a601 ld a,#1
2636 036d 6b01 ld (OFST+0,sp),a
2638 036f 2015 jra L7331
2639 0371 L3331:
2640 ; 746 bitstatus = RESET;
2642 0371 0f01 clr (OFST+0,sp)
2643 0373 2011 jra L7331
2644 0375 L1331:
2645 ; 752 if ((CLK->CSSR & (u8)CLK_IT) == (u8)0x0C)
2647 0375 c650c8 ld a,20680
2648 0378 1402 and a,(OFST+1,sp)
2649 037a a10c cp a,#12
2650 037c 2606 jrne L1431
2651 ; 754 bitstatus = SET;
2653 037e a601 ld a,#1
2654 0380 6b01 ld (OFST+0,sp),a
2656 0382 2002 jra L7331
2657 0384 L1431:
2658 ; 758 bitstatus = RESET;
2660 0384 0f01 clr (OFST+0,sp)
2661 0386 L7331:
2662 ; 763 return bitstatus;
2664 0386 7b01 ld a,(OFST+0,sp)
2667 0388 85 popw x
2668 0389 81 ret
2704 ; 773 void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT)
2704 ; 774 {
2705 switch .text
2706 038a _CLK_ClearITPendingBit:
2710 ; 777 assert_param(IS_CLK_IT_OK(CLK_IT));
2712 ; 779 if (CLK_IT == (u8)CLK_IT_CSSD)
2714 038a a10c cp a,#12
2715 038c 2606 jrne L3631
2716 ; 782 CLK->CSSR &= (u8)(~CLK_CSSR_CSSD);
2718 038e 721750c8 bres 20680,#3
2720 0392 2004 jra L5631
2721 0394 L3631:
2722 ; 787 CLK->SWCR &= (u8)(~CLK_SWCR_SWIF);
2724 0394 721750c5 bres 20677,#3
2725 0398 L5631:
2726 ; 790 }
2729 0398 81 ret
2764 xdef _CLKPrescTable
2765 xdef _HSIDivFactor
2766 xdef _CLK_ClearITPendingBit
2767 xdef _CLK_GetITStatus
2768 xdef _CLK_GetFlagStatus
2769 xdef _CLK_GetSYSCLKSource
2770 xdef _CLK_GetClockFreq
2771 xdef _CLK_AdjustHSICalibrationValue
2772 xdef _CLK_SYSCLKEmergencyClear
2773 xdef _CLK_ClockSecuritySystemEnable
2774 xdef _CLK_CANConfig
2775 xdef _CLK_SWIMConfig
2776 xdef _CLK_SYSCLKConfig
2777 xdef _CLK_ITConfig
2778 xdef _CLK_CCOConfig
2779 xdef _CLK_HSIPrescalerConfig
2780 xdef _CLK_ClockSwitchConfig
2781 xdef _CLK_PeripheralClockConfig
2782 xdef _CLK_SlowActiveHaltWakeUpCmd
2783 xdef _CLK_FastHaltWakeUpCmd
2784 xdef _CLK_ClockSwitchCmd
2785 xdef _CLK_CCOCmd
2786 xdef _CLK_LSICmd
2787 xdef _CLK_HSICmd
2788 xdef _CLK_HSECmd
2789 xdef _CLK_DeInit
2790 xref.b c_lreg
2791 xref.b c_x
2810 xref c_ludv
2811 xref c_rtol
2812 xref c_ltor
2813 end
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