📄 stm8s_clk.ls
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1027 011a 7b05 ld a,(OFST+1,sp)
1028 011c a101 cp a,#1
1029 011e 2639 jrne L544
1030 ; 339 CLK->SWCR |= CLK_SWCR_SWEN;
1032 0120 721250c5 bset 20677,#1
1033 ; 342 if (ITState != DISABLE)
1035 0124 0d09 tnz (OFST+5,sp)
1036 0126 2706 jreq L744
1037 ; 344 CLK->SWCR |= CLK_SWCR_SWIEN;
1039 0128 721450c5 bset 20677,#2
1041 012c 2004 jra L154
1042 012e L744:
1043 ; 348 CLK->SWCR &= (u8)(~CLK_SWCR_SWIEN);
1045 012e 721550c5 bres 20677,#2
1046 0132 L154:
1047 ; 352 CLK->SWR = (u8)CLK_NewClock;
1049 0132 7b06 ld a,(OFST+2,sp)
1050 0134 c750c4 ld 20676,a
1052 0137 2007 jra L754
1053 0139 L354:
1054 ; 356 DownCounter--;
1056 0139 1e03 ldw x,(OFST-1,sp)
1057 013b 1d0001 subw x,#1
1058 013e 1f03 ldw (OFST-1,sp),x
1059 0140 L754:
1060 ; 354 while (((CLK->SWCR & CLK_SWCR_SWBSY) && (DownCounter != 0)))
1062 0140 c650c5 ld a,20677
1063 0143 a501 bcp a,#1
1064 0145 2704 jreq L364
1066 0147 1e03 ldw x,(OFST-1,sp)
1067 0149 26ee jrne L354
1068 014b L364:
1069 ; 359 if (DownCounter != 0)
1071 014b 1e03 ldw x,(OFST-1,sp)
1072 014d 2706 jreq L564
1073 ; 361 Swif = SUCCESS;
1075 014f a601 ld a,#1
1076 0151 6b02 ld (OFST-2,sp),a
1078 0153 201b jra L174
1079 0155 L564:
1080 ; 365 Swif = ERROR;
1082 0155 0f02 clr (OFST-2,sp)
1083 0157 2017 jra L174
1084 0159 L544:
1085 ; 373 if (ITState != DISABLE)
1087 0159 0d09 tnz (OFST+5,sp)
1088 015b 2706 jreq L374
1089 ; 375 CLK->SWCR |= CLK_SWCR_SWIEN;
1091 015d 721450c5 bset 20677,#2
1093 0161 2004 jra L574
1094 0163 L374:
1095 ; 379 CLK->SWCR &= (u8)(~CLK_SWCR_SWIEN);
1097 0163 721550c5 bres 20677,#2
1098 0167 L574:
1099 ; 383 CLK->SWR = (u8)CLK_NewClock;
1101 0167 7b06 ld a,(OFST+2,sp)
1102 0169 c750c4 ld 20676,a
1103 ; 387 Swif = SUCCESS;
1105 016c a601 ld a,#1
1106 016e 6b02 ld (OFST-2,sp),a
1107 0170 L174:
1108 ; 392 if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSI))
1110 0170 0d0a tnz (OFST+6,sp)
1111 0172 260c jrne L774
1113 0174 7b01 ld a,(OFST-3,sp)
1114 0176 a1e1 cp a,#225
1115 0178 2606 jrne L774
1116 ; 394 CLK->ICKR &= (u8)(~CLK_ICKR_HSIEN);
1118 017a 721150c0 bres 20672,#0
1120 017e 201e jra L105
1121 0180 L774:
1122 ; 396 else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_LSI))
1124 0180 0d0a tnz (OFST+6,sp)
1125 0182 260c jrne L305
1127 0184 7b01 ld a,(OFST-3,sp)
1128 0186 a1d2 cp a,#210
1129 0188 2606 jrne L305
1130 ; 398 CLK->ICKR &= (u8)(~CLK_ICKR_LSIEN);
1132 018a 721750c0 bres 20672,#3
1134 018e 200e jra L105
1135 0190 L305:
1136 ; 400 else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSE))
1138 0190 0d0a tnz (OFST+6,sp)
1139 0192 260a jrne L105
1141 0194 7b01 ld a,(OFST-3,sp)
1142 0196 a1b4 cp a,#180
1143 0198 2604 jrne L105
1144 ; 402 CLK->ECKR &= (u8)(~CLK_ECKR_HSEEN);
1146 019a 721150c1 bres 20673,#0
1147 019e L105:
1148 ; 405 return(Swif);
1150 019e 7b02 ld a,(OFST-2,sp)
1153 01a0 5b06 addw sp,#6
1154 01a2 81 ret
1292 ; 415 void CLK_HSIPrescalerConfig(CLK_Prescaler_TypeDef HSIPrescaler)
1292 ; 416 {
1293 switch .text
1294 01a3 _CLK_HSIPrescalerConfig:
1296 01a3 88 push a
1297 00000000 OFST: set 0
1300 ; 419 assert_param(IS_CLK_HSIPRESCALER_OK(HSIPrescaler));
1302 ; 422 CLK->CKDIVR &= (u8)(~CLK_CKDIVR_HSIDIV);
1304 01a4 c650c6 ld a,20678
1305 01a7 a4e7 and a,#231
1306 01a9 c750c6 ld 20678,a
1307 ; 425 CLK->CKDIVR |= (u8)HSIPrescaler;
1309 01ac c650c6 ld a,20678
1310 01af 1a01 or a,(OFST+1,sp)
1311 01b1 c750c6 ld 20678,a
1312 ; 427 }
1315 01b4 84 pop a
1316 01b5 81 ret
1451 ; 438 void CLK_CCOConfig(CLK_Output_TypeDef CLK_CCO)
1451 ; 439 {
1452 switch .text
1453 01b6 _CLK_CCOConfig:
1455 01b6 88 push a
1456 00000000 OFST: set 0
1459 ; 442 assert_param(IS_CLK_OUTPUT_OK(CLK_CCO));
1461 ; 445 CLK->CCOR &= (u8)(~CLK_CCOR_CCOSEL);
1463 01b7 c650c9 ld a,20681
1464 01ba a4e1 and a,#225
1465 01bc c750c9 ld 20681,a
1466 ; 448 CLK->CCOR |= (u8)CLK_CCO;
1468 01bf c650c9 ld a,20681
1469 01c2 1a01 or a,(OFST+1,sp)
1470 01c4 c750c9 ld 20681,a
1471 ; 451 CLK->CCOR |= CLK_CCOR_CCOEN;
1473 01c7 721050c9 bset 20681,#0
1474 ; 453 }
1477 01cb 84 pop a
1478 01cc 81 ret
1543 ; 463 void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
1543 ; 464 {
1544 switch .text
1545 01cd _CLK_ITConfig:
1547 01cd 89 pushw x
1548 00000000 OFST: set 0
1551 ; 467 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1553 ; 468 assert_param(IS_CLK_IT_OK(CLK_IT));
1555 ; 470 if (NewState != DISABLE)
1557 01ce 9f ld a,xl
1558 01cf 4d tnz a
1559 01d0 2719 jreq L507
1560 ; 473 switch (CLK_IT)
1562 01d2 9e ld a,xh
1564 ; 481 default:
1564 ; 482 break;
1565 01d3 a00c sub a,#12
1566 01d5 270a jreq L146
1567 01d7 a010 sub a,#16
1568 01d9 2624 jrne L317
1569 ; 475 case CLK_IT_SWIF: /* Enable the clock switch interrupt */
1569 ; 476 CLK->SWCR |= CLK_SWCR_SWIEN;
1571 01db 721450c5 bset 20677,#2
1572 ; 477 break;
1574 01df 201e jra L317
1575 01e1 L146:
1576 ; 478 case CLK_IT_CSSD: /* Enable the clock security system detection interrupt */
1576 ; 479 CLK->CSSR |= CLK_CSSR_CSSDIE;
1578 01e1 721450c8 bset 20680,#2
1579 ; 480 break;
1581 01e5 2018 jra L317
1582 01e7 L346:
1583 ; 481 default:
1583 ; 482 break;
1585 01e7 2016 jra L317
1586 01e9 L117:
1588 01e9 2014 jra L317
1589 01eb L507:
1590 ; 487 switch (CLK_IT)
1592 01eb 7b01 ld a,(OFST+1,sp)
1594 ; 495 default:
1594 ; 496 break;
1595 01ed a00c sub a,#12
1596 01ef 270a jreq L746
1597 01f1 a010 sub a,#16
1598 01f3 260a jrne L317
1599 ; 489 case CLK_IT_SWIF: /* Disable the clock switch interrupt */
1599 ; 490 CLK->SWCR &= (u8)(~CLK_SWCR_SWIEN);
1601 01f5 721550c5 bres 20677,#2
1602 ; 491 break;
1604 01f9 2004 jra L317
1605 01fb L746:
1606 ; 492 case CLK_IT_CSSD: /* Disable the clock security system detection interrupt */
1606 ; 493 CLK->CSSR &= (u8)(~CLK_CSSR_CSSDIE);
1608 01fb 721550c8 bres 20680,#2
1609 ; 494 break;
1610 01ff L317:
1611 ; 500 }
1614 01ff 85 popw x
1615 0200 81 ret
1616 0201 L156:
1617 ; 495 default:
1617 ; 496 break;
1619 0201 20fc jra L317
1620 0203 L717:
1621 0203 20fa jra L317
1656 ; 507 void CLK_SYSCLKConfig(CLK_Prescaler_TypeDef ClockPrescaler)
1656 ; 508 {
1657 switch .text
1658 0205 _CLK_SYSCLKConfig:
1660 0205 88 push a
1661 00000000 OFST: set 0
1664 ; 511 assert_param(IS_CLK_PRESCALER_OK(ClockPrescaler));
1666 ; 513 if (((u8)ClockPrescaler & (u8)0x80) == 0x00) /* Bit7 = 0 means HSI divider */
1668 0206 a580 bcp a,#128
1669 0208 2614 jrne L737
1670 ; 515 CLK->CKDIVR &= (u8)(~CLK_CKDIVR_HSIDIV);
1672 020a c650c6 ld a,20678
1673 020d a4e7 and a,#231
1674 020f c750c6 ld 20678,a
1675 ; 516 CLK->CKDIVR |= (u8)((u8)ClockPrescaler & (u8)CLK_CKDIVR_HSIDIV);
1677 0212 7b01 ld a,(OFST+1,sp)
1678 0214 a418 and a,#24
1679 0216 ca50c6 or a,20678
1680 0219 c750c6 ld 20678,a
1682 021c 2012 jra L147
1683 021e L737:
1684 ; 520 CLK->CKDIVR &= (u8)(~CLK_CKDIVR_CPUDIV);
1686 021e c650c6 ld a,20678
1687 0221 a4f8 and a,#248
1688 0223 c750c6 ld 20678,a
1689 ; 521 CLK->CKDIVR |= (u8)((u8)ClockPrescaler & (u8)CLK_CKDIVR_CPUDIV);
1691 0226 7b01 ld a,(OFST+1,sp)
1692 0228 a407 and a,#7
1693 022a ca50c6 or a,20678
1694 022d c750c6 ld 20678,a
1695 0230 L147:
1696 ; 524 }
1699 0230 84 pop a
1700 0231 81 ret
1756 ; 531 void CLK_SWIMConfig(CLK_SWIMDivider_TypeDef CLK_SWIMDivider)
1756 ; 532 {
1757 switch .text
1758 0232 _CLK_SWIMConfig:
1762 ; 535 assert_param(IS_CLK_SWIMDIVIDER_OK(CLK_SWIMDivider));
1764 ; 537 if (CLK_SWIMDivider != CLK_SWIMDIVIDER_2)
1766 0232 4d tnz a
1767 0233 2706 jreq L177
1768 ; 540 CLK->SWIMCCR |= CLK_SWIMCCR_SWIMDIV;
1770 0235 721050cd bset 20685,#0
1772 0239 2004 jra L377
1773 023b L177:
1774 ; 545 CLK->SWIMCCR &= (u8)(~CLK_SWIMCCR_SWIMDIV);
1776 023b 721150cd bres 20685,#0
1777 023f L377:
1778 ; 548 }
1781 023f 81 ret
1878 ; 556 void CLK_CANConfig(CLK_CANDivider_TypeDef CLK_CANDivider)
1878 ; 557 {
1879 switch .text
1880 0240 _CLK_CANConfig:
1882 0240 88 push a
1883 00000000 OFST: set 0
1886 ; 560 assert_param(IS_CLK_CANDIVIDER_OK(CLK_CANDivider));
1888 ; 563 CLK->CANCCR &= (u8)(~CLK_CANCCR_CANDIV);
1890 0241 c650cb ld a,20683
1891 0244 a4f8 and a,#248
1892 0246 c750cb ld 20683,a
1893 ; 566 CLK->CANCCR |= (u8)CLK_CANDivider;
1895 0249 c650cb ld a,20683
1896 024c 1a01 or a,(OFST+1,sp)
1897 024e c750cb ld 20683,a
1898 ; 568 }
1901 0251 84 pop a
1902 0252 81 ret
1926 ; 578 void CLK_ClockSecuritySystemEnable(void)
1926 ; 579 {
1927 switch .text
1928 0253 _CLK_ClockSecuritySystemEnable:
1932 ; 581 CLK->CSSR |= CLK_CSSR_CSSEN;
1934 0253 721050c8 bset 20680,#0
1935 ; 582 }
1938 0257 81 ret
1963 ; 591 CLK_Source_TypeDef CLK_GetSYSCLKSource(void)
1963 ; 592 {
1964 switch .text
1965 0258 _CLK_GetSYSCLKSource:
1969 ; 593 return((CLK_Source_TypeDef)CLK->CMSR);
1971 0258 c650c3 ld a,20675
1974 025b 81 ret
2037 ; 603 u32 CLK_GetClockFreq(void)
2037 ; 604 {
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