stm8s_tim5.c

STM8s

    assert_param(IS_TIM5_IT_OK(TIM5_IT));
    assert_param(IS_FUNCTIONALSTATE_OK(NewState));

    if (NewState != DISABLE)
    {
        /* Enable the Interrupt sources */
        TIM5->IER |= (u8)TIM5_IT;
    }
    else
    {
        /* Disable the Interrupt sources */
        TIM5->IER &= (u8)(~TIM5_IT);
    }
}


/**
  * @brief Enables or Disables the TIM5 Update event.
  * @param[in] NewState new state of the TIM5 peripheral Preload register.This parameter can
  * be ENABLE or DISABLE.
  * @retval None
  */
void TIM5_UpdateDisableConfig(FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_FUNCTIONALSTATE_OK(NewState));

    /* Set or Reset the UDIS Bit */
    if (NewState != DISABLE)
    {
        TIM5->CR1 |= TIM5_CR1_UDIS ;
    }
    else
    {
        TIM5->CR1 &= (u8)(~TIM5_CR1_UDIS) ;
    }
}

/**
  * @brief Selects the TIM5 Update Request Interrupt source.
  * @param[in] TIM5_UpdateSource specifies the Update source.
  * This parameter can be one of the following values
  *                       - TIM5_UPDATESOURCE_REGULAR
  *                       - TIM5_UPDATESOURCE_GLOBAL
  * @retval None
  */
void TIM5_UpdateRequestConfig(TIM5_UpdateSource_TypeDef TIM5_UpdateSource)
{
    /* Check the parameters */
    assert_param(IS_TIM5_UPDATE_SOURCE_OK(TIM5_UpdateSource));

    /* Set or Reset the URS Bit */
    if (TIM5_UpdateSource != TIM5_UPDATESOURCE_GLOBAL)
    {
        TIM5->CR1 |= TIM5_CR1_URS ;
    }
    else
    {
        TIM5->CR1 &= (u8)(~TIM5_CR1_URS) ;
    }
}


/**
  * @brief Selects the TIM5抯 One Pulse Mode.
  * @param[in] TIM5_OPMode specifies the OPM Mode to be used.
  * This parameter can be one of the following values
  *                    - TIM5_OPMODE_SINGLE
  *                    - TIM5_OPMODE_REPETITIVE
  * @retval None
  */
void TIM5_SelectOnePulseMode(TIM5_OPMode_TypeDef TIM5_OPMode)
{
    /* Check the parameters */
    assert_param(IS_TIM5_OPM_MODE_OK(TIM5_OPMode));

    /* Set or Reset the OPM Bit */
    if (TIM5_OPMode != TIM5_OPMODE_REPETITIVE)
    {
        TIM5->CR1 |= TIM5_CR1_OPM ;
    }
    else
    {
        TIM5->CR1 &= (u8)(~TIM5_CR1_OPM) ;
    }

}


/**
  * @brief Configures the TIM5 Prescaler.
  * @param[in] Prescaler specifies the Prescaler Register value
  * This parameter can be one of the following values
  *                       -  TIM5_PRESCALER_1
  *                       -  TIM5_PRESCALER_2
  *                       -  TIM5_PRESCALER_4
  *                       -  TIM5_PRESCALER_8
  *                       -  TIM5_PRESCALER_16
  *                       -  TIM5_PRESCALER_32
  *                       -  TIM5_PRESCALER_64
  *                       -  TIM5_PRESCALER_128
  *                       -  TIM5_PRESCALER_256
  *                       -  TIM5_PRESCALER_512
  *                       -  TIM5_PRESCALER_1024
  *                       -  TIM5_PRESCALER_2048
  *                       -  TIM5_PRESCALER_4096
  *                       -  TIM5_PRESCALER_8192
  *                       -  TIM5_PRESCALER_16384
  *                       -  TIM5_PRESCALER_32768
  * @param[in] TIM5_PSCReloadMode specifies the TIM5 Prescaler Reload mode.
  * This parameter can be one of the following values
  *                       - TIM5_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded
  *                         immediatly.
  *                       - TIM5_PSCRELOADMODE_UPDATE: The Prescaler is loaded at
  *                         the update event.
  * @retval None
  */
void TIM5_PrescalerConfig(TIM5_Prescaler_TypeDef Prescaler,
                          TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode)
{
    /* Check the parameters */
    assert_param(IS_TIM5_PRESCALER_RELOAD_OK(TIM5_PSCReloadMode));
    assert_param(IS_TIM5_PRESCALER_OK(Prescaler));

    /* Set the Prescaler value */
    TIM5->PSCR = (u8)Prescaler;

    /* Set or reset the UG Bit */
    TIM5->EGR = (u8)TIM5_PSCReloadMode ;
}

/**
  * @brief Forces the TIM5 Channel1 output waveform to active or inactive level.
  * @param[in] TIM5_ForcedAction specifies the forced Action to be set to the output waveform.
  * This parameter can be one of the following values:
  *                       - TIM5_FORCEDACTION_ACTIVE: Force active level on OC1REF
  *                       - TIM5_FORCEDACTION_INACTIVE: Force inactive level on
  *                         OC1REF.
  * @retval None
  */
void TIM5_ForcedOC1Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
{
    /* Check the parameters */
    assert_param(IS_TIM5_FORCED_ACTION_OK(TIM5_ForcedAction));

    /* Reset the OCM Bits */ /* Configure The Forced output Mode */
    TIM5->CCMR1  =  (u8)((TIM5->CCMR1 & (u8)(~TIM5_CCMR_OCM))  | (u8)TIM5_ForcedAction);
}

/**
  * @brief Forces the TIM5 Channel2 output waveform to active or inactive level.
  * @param[in] TIM5_ForcedAction specifies the forced Action to be set to the output waveform.
  * This parameter can be one of the following values:
  *                       - TIM5_FORCEDACTION_ACTIVE: Force active level on OC2REF
  *                       - TIM5_FORCEDACTION_INACTIVE: Force inactive level on
  *                         OC2REF.
  * @retval None
  */
void TIM5_ForcedOC2Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
{
    /* Check the parameters */
    assert_param(IS_TIM5_FORCED_ACTION_OK(TIM5_ForcedAction));

    /* Reset the OCM Bits */ /* Configure The Forced output Mode */
    TIM5->CCMR2  =  (u8)((TIM5->CCMR2 & (u8)(~TIM5_CCMR_OCM))  | (u8)TIM5_ForcedAction);
}

/**
  * @brief Forces the TIM5 Channel3 output waveform to active or inactive level.
  * @param[in] TIM5_ForcedAction specifies the forced Action to be set to the output waveform.
  * This parameter can be one of the following values:
  *                       - TIM5_FORCEDACTION_ACTIVE: Force active level on OC3REF
  *                       - TIM5_FORCEDACTION_INACTIVE: Force inactive level on
  *                         OC3REF.
  * @retval None
  */
void TIM5_ForcedOC3Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction)
{
    /* Check the parameters */
    assert_param(IS_TIM5_FORCED_ACTION_OK(TIM5_ForcedAction));

    /* Reset the OCM Bits */ /* Configure The Forced output Mode */
    TIM5->CCMR3  =  (u8)((TIM5->CCMR3 & (u8)(~TIM5_CCMR_OCM))  | (u8)TIM5_ForcedAction);
}


/**
  * @brief Enables or disables TIM5 peripheral Preload register on ARR.
  * @param[in] NewState new state of the TIM5 peripheral Preload register.
  * This parameter can be ENABLE or DISABLE.
  * @retval None
  */
void TIM5_ARRPreloadConfig(FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_FUNCTIONALSTATE_OK(NewState));

    /* Set or Reset the ARPE Bit */
    if (NewState != DISABLE)
    {
        TIM5->CR1 |= TIM5_CR1_ARPE ;
    }
    else
    {
        TIM5->CR1 &= (u8)(~TIM5_CR1_ARPE) ;
    }
}


/**
  * @brief Enables or disables the TIM5 peripheral Preload Register on CCR1.
  * @param[in] NewState new state of the Capture Compare Preload register.
  * This parameter can be ENABLE or DISABLE.
  * @retval None
  */
void TIM5_OC1PreloadConfig(FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_FUNCTIONALSTATE_OK(NewState));

    /* Set or Reset the OC1PE Bit */
    if (NewState != DISABLE)
    {
        TIM5->CCMR1 |= TIM5_CCMR_OCxPE ;
    }
    else
    {
        TIM5->CCMR1 &= (u8)(~TIM5_CCMR_OCxPE) ;
    }
}


/**
  * @brief Enables or disables the TIM5 peripheral Preload Register on CCR2.
  * @param[in] NewState new state of the Capture Compare Preload register.
  * This parameter can be ENABLE or DISABLE.
  * @retval None
  */
void TIM5_OC2PreloadConfig(FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_FUNCTIONALSTATE_OK(NewState));

    /* Set or Reset the OC2PE Bit */
    if (NewState != DISABLE)
    {
        TIM5->CCMR2 |= TIM5_CCMR_OCxPE ;
    }
    else
    {
        TIM5->CCMR2 &= (u8)(~TIM5_CCMR_OCxPE) ;
    }
}


/**
  * @brief Enables or disables the TIM5 peripheral Preload Register on CCR3.
  * @param[in] NewState new state of the Capture Compare Preload register.
  * This parameter can be ENABLE or DISABLE.
  * @retval None
  */
void TIM5_OC3PreloadConfig(FunctionalState NewState)
{
    /* Check the parameters */
    assert_param(IS_FUNCTIONALSTATE_OK(NewState));

    /* Set or Reset the OC3PE Bit */
    if (NewState != DISABLE)
    {
        TIM5->CCMR3 |= TIM5_CCMR_OCxPE ;
    }
    else
    {
        TIM5->CCMR3 &= (u8)(~TIM5_CCMR_OCxPE) ;
    }
}


/**
  * @brief Configures the TIM5 event to be generated by software.
  * @param[in] TIM5_EventSource specifies the event source.
  * This parameter can be one of the following values:
  *                       - TIM5_EVENTSOURCE_UPDATE: TIM5 update Event source
  *                       - TIM5_EVENTSOURCE_CC1: TIM5 Capture Compare 1 Event source
  *                       - TIM5_EVENTSOURCE_CC2: TIM5 Capture Compare 2 Event source
  *                       - TIM5_EVENTSOURCE_CC3: TIM5 Capture Compare 3 Event source
  * @retval None
  */
void TIM5_GenerateEvent(TIM5_EventSource_TypeDef TIM5_EventSource)
{
    /* Check the parameters */
    assert_param(IS_TIM5_EVENT_SOURCE_OK(TIM5_EventSource));

    /* Set the event sources */
    TIM5->EGR = (u8)TIM5_EventSource;
}


/**
  * @brief Configures the TIM5 Channel 1 polarity.
  * @param[in] TIM5_OCPolarity specifies the OC1 Polarity.
  * This parameter can be one of the following values:
  *                       - TIM5_OCPOLARITY_LOW: Output Compare active low
  *                       - TIM5_OCPOLARITY_HIGH: Output Compare active high
  * @retval None
  */
void TIM5_OC1PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
{
    /* Check the parameters */
    assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));

    /* Set or Reset the CC1P Bit */
    if (TIM5_OCPolarity != TIM5_OCPOLARITY_HIGH)
    {
        TIM5->CCER1 |= TIM5_CCER1_CC1P ;
    }
    else
    {
        TIM5->CCER1 &= (u8)(~TIM5_CCER1_CC1P) ;
    }
}


/**
  * @brief Configures the TIM5 Channel 2 polarity.
  * @param[in] TIM5_OCPolarity specifies the OC2 Polarity.
  * This parameter can be one of the following values:
  *                       - TIM5_OCPOLARITY_LOW: Output Compare active low
  *                       - TIM5_OCPOLARITY_HIGH: Output Compare active high
  * @retval None
  */
void TIM5_OC2PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
{
    /* Check the parameters */
    assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));

    /* Set or Reset the CC2P Bit */
    if (TIM5_OCPolarity != TIM5_OCPOLARITY_HIGH)
    {
        TIM5->CCER1 |= TIM5_CCER1_CC2P ;
    }
    else
    {
        TIM5->CCER1 &= (u8)(~TIM5_CCER1_CC2P) ;
    }
}


/**
  * @brief Configures the TIM5 Channel 3 polarity.
  * @param[in] TIM5_OCPolarity specifies the OC3 Polarity.
  * This parameter can be one of the following values:
  *                       - TIM5_OCPOLARITY_LOW: Output Compare active low
  *                       - TIM5_OCPOLARITY_HIGH: Output Compare active high
  * @retval None
  */
void TIM5_OC3PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity)
{
    /* Check the parameters */
    assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity));

    /* Set or Reset the CC3P Bit */
    if (TIM5_OCPolarity != TIM5_OCPOLARITY_HIGH)
    {
        TIM5->CCER2 |= TIM5_CCER2_CC3P ;
    }
    else