📄 stm8s_tim3.ls
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2799 02f8 1a03 or a,(OFST-1,sp)
2800 02fa 01 rrwa x,a
2801 02fb 1f03 ldw (OFST-1,sp),x
2802 ; 836 return (u16)tmpccr2;
2804 02fd 1e03 ldw x,(OFST-1,sp)
2807 02ff 5b04 addw sp,#4
2808 0301 81 ret
2831 ; 845 u16 TIM3_GetCounter(void)
2831 ; 846 {
2832 switch .text
2833 0302 _TIM3_GetCounter:
2835 0302 89 pushw x
2836 00000002 OFST: set 2
2839 ; 848 return (u16)(((u16)TIM3->CNTRH << 8) | (u16)(TIM3->CNTRL));
2841 0303 c65329 ld a,21289
2842 0306 5f clrw x
2843 0307 97 ld xl,a
2844 0308 1f01 ldw (OFST-1,sp),x
2845 030a c65328 ld a,21288
2846 030d 5f clrw x
2847 030e 97 ld xl,a
2848 030f 4f clr a
2849 0310 02 rlwa x,a
2850 0311 01 rrwa x,a
2851 0312 1a02 or a,(OFST+0,sp)
2852 0314 01 rrwa x,a
2853 0315 1a01 or a,(OFST-1,sp)
2854 0317 01 rrwa x,a
2857 0318 5b02 addw sp,#2
2858 031a 81 ret
2882 ; 858 TIM3_Prescaler_TypeDef TIM3_GetPrescaler(void)
2882 ; 859 {
2883 switch .text
2884 031b _TIM3_GetPrescaler:
2888 ; 861 return (TIM3_Prescaler_TypeDef)(TIM3->PSCR);
2890 031b c6532a ld a,21290
2893 031e 81 ret
3018 ; 876 FlagStatus TIM3_GetFlagStatus(TIM3_FLAG_TypeDef TIM3_FLAG)
3018 ; 877 {
3019 switch .text
3020 031f _TIM3_GetFlagStatus:
3022 031f 5204 subw sp,#4
3023 00000004 OFST: set 4
3026 ; 878 volatile FlagStatus bitstatus = RESET;
3028 0321 0f04 clr (OFST+0,sp)
3029 ; 882 assert_param(IS_TIM3_GET_FLAG_OK(TIM3_FLAG));
3031 ; 884 tim3_flag_l = (u8)(TIM3_FLAG);
3033 0323 9f ld a,xl
3034 0324 6b02 ld (OFST-2,sp),a
3035 ; 885 tim3_flag_h = (u8)(TIM3_FLAG >> 8);
3037 0326 9e ld a,xh
3038 0327 6b03 ld (OFST-1,sp),a
3039 ; 887 if (((TIM3->SR1 & tim3_flag_l) | (TIM3->SR2 & tim3_flag_h)) != (u8)RESET )
3041 0329 c65323 ld a,21283
3042 032c 1403 and a,(OFST-1,sp)
3043 032e 6b01 ld (OFST-3,sp),a
3044 0330 c65322 ld a,21282
3045 0333 1402 and a,(OFST-2,sp)
3046 0335 1a01 or a,(OFST-3,sp)
3047 0337 2706 jreq L5741
3048 ; 889 bitstatus = SET;
3050 0339 a601 ld a,#1
3051 033b 6b04 ld (OFST+0,sp),a
3053 033d 2002 jra L7741
3054 033f L5741:
3055 ; 893 bitstatus = RESET;
3057 033f 0f04 clr (OFST+0,sp)
3058 0341 L7741:
3059 ; 895 return (FlagStatus)bitstatus;
3061 0341 7b04 ld a,(OFST+0,sp)
3064 0343 5b04 addw sp,#4
3065 0345 81 ret
3100 ; 910 void TIM3_ClearFlag(TIM3_FLAG_TypeDef TIM3_FLAG)
3100 ; 911 {
3101 switch .text
3102 0346 _TIM3_ClearFlag:
3104 0346 89 pushw x
3105 00000000 OFST: set 0
3108 ; 913 assert_param(IS_TIM3_CLEAR_FLAG_OK(TIM3_FLAG));
3110 ; 916 TIM3->SR1 = (u8)(~((u8)(TIM3_FLAG)));
3112 0347 9f ld a,xl
3113 0348 43 cpl a
3114 0349 c75322 ld 21282,a
3115 ; 917 TIM3->SR2 = (u8)(~((u8)(TIM3_FLAG >> 8)));
3117 034c 7b01 ld a,(OFST+1,sp)
3118 034e 43 cpl a
3119 034f c75323 ld 21283,a
3120 ; 918 }
3123 0352 85 popw x
3124 0353 81 ret
3188 ; 931 ITStatus TIM3_GetITStatus(TIM3_IT_TypeDef TIM3_IT)
3188 ; 932 {
3189 switch .text
3190 0354 _TIM3_GetITStatus:
3192 0354 88 push a
3193 0355 5203 subw sp,#3
3194 00000003 OFST: set 3
3197 ; 933 volatile ITStatus bitstatus = RESET;
3199 0357 0f03 clr (OFST+0,sp)
3200 ; 934 vu8 TIM3_itStatus = 0, TIM3_itEnable = 0;
3202 0359 0f01 clr (OFST-2,sp)
3205 035b 0f02 clr (OFST-1,sp)
3206 ; 937 assert_param(IS_TIM3_GET_IT_OK(TIM3_IT));
3208 ; 939 TIM3_itStatus = (u8)(TIM3->SR1 & TIM3_IT);
3210 035d c45322 and a,21282
3211 0360 6b01 ld (OFST-2,sp),a
3212 ; 941 TIM3_itEnable = (u8)(TIM3->IER & TIM3_IT);
3214 0362 c65321 ld a,21281
3215 0365 1404 and a,(OFST+1,sp)
3216 0367 6b02 ld (OFST-1,sp),a
3217 ; 943 if ((TIM3_itStatus != (u8)RESET ) && (TIM3_itEnable != (u8)RESET ))
3219 0369 0d01 tnz (OFST-2,sp)
3220 036b 270a jreq L1551
3222 036d 0d02 tnz (OFST-1,sp)
3223 036f 2706 jreq L1551
3224 ; 945 bitstatus = SET;
3226 0371 a601 ld a,#1
3227 0373 6b03 ld (OFST+0,sp),a
3229 0375 2002 jra L3551
3230 0377 L1551:
3231 ; 949 bitstatus = RESET;
3233 0377 0f03 clr (OFST+0,sp)
3234 0379 L3551:
3235 ; 951 return (ITStatus)(bitstatus);
3237 0379 7b03 ld a,(OFST+0,sp)
3240 037b 5b04 addw sp,#4
3241 037d 81 ret
3277 ; 964 void TIM3_ClearITPendingBit(TIM3_IT_TypeDef TIM3_IT)
3277 ; 965 {
3278 switch .text
3279 037e _TIM3_ClearITPendingBit:
3283 ; 967 assert_param(IS_TIM3_IT_OK(TIM3_IT));
3285 ; 970 TIM3->SR1 = (u8)(~TIM3_IT);
3287 037e 43 cpl a
3288 037f c75322 ld 21282,a
3289 ; 971 }
3292 0382 81 ret
3344 ; 990 static void TI1_Config(u8 TIM3_ICPolarity,
3344 ; 991 u8 TIM3_ICSelection,
3344 ; 992 u8 TIM3_ICFilter)
3344 ; 993 {
3345 switch .text
3346 0383 L3_TI1_Config:
3348 0383 89 pushw x
3349 0384 88 push a
3350 00000001 OFST: set 1
3353 ; 995 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC1E);
3355 0385 72115327 bres 21287,#0
3356 ; 998 TIM3->CCMR1 = (u8)((TIM3->CCMR1 & (u8)(~( TIM3_CCMR_CCxS | TIM3_CCMR_ICxF ))) | (u8)(( (TIM3_ICSelection)) | ((u8)( TIM3_ICFilter << 4))));
3358 0389 7b06 ld a,(OFST+5,sp)
3359 038b 97 ld xl,a
3360 038c a610 ld a,#16
3361 038e 42 mul x,a
3362 038f 9f ld a,xl
3363 0390 1a03 or a,(OFST+2,sp)
3364 0392 6b01 ld (OFST+0,sp),a
3365 0394 c65325 ld a,21285
3366 0397 a40c and a,#12
3367 0399 1a01 or a,(OFST+0,sp)
3368 039b c75325 ld 21285,a
3369 ; 1001 if (TIM3_ICPolarity != TIM3_ICPOLARITY_RISING)
3371 039e 0d02 tnz (OFST+1,sp)
3372 03a0 2706 jreq L1261
3373 ; 1003 TIM3->CCER1 |= TIM3_CCER1_CC1P;
3375 03a2 72125327 bset 21287,#1
3377 03a6 2004 jra L3261
3378 03a8 L1261:
3379 ; 1007 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC1P);
3381 03a8 72135327 bres 21287,#1
3382 03ac L3261:
3383 ; 1010 TIM3->CCER1 |= TIM3_CCER1_CC1E;
3385 03ac 72105327 bset 21287,#0
3386 ; 1011 }
3389 03b0 5b03 addw sp,#3
3390 03b2 81 ret
3442 ; 1030 static void TI2_Config(u8 TIM3_ICPolarity,
3442 ; 1031 u8 TIM3_ICSelection,
3442 ; 1032 u8 TIM3_ICFilter)
3442 ; 1033 {
3443 switch .text
3444 03b3 L5_TI2_Config:
3446 03b3 89 pushw x
3447 03b4 88 push a
3448 00000001 OFST: set 1
3451 ; 1035 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC2E);
3453 03b5 72195327 bres 21287,#4
3454 ; 1038 TIM3->CCMR2 = (u8)((TIM3->CCMR2 & (u8)(~( TIM3_CCMR_CCxS | TIM3_CCMR_ICxF ))) | (u8)(( (TIM3_ICSelection)) | ((u8)( TIM3_ICFilter << 4))));
3456 03b9 7b06 ld a,(OFST+5,sp)
3457 03bb 97 ld xl,a
3458 03bc a610 ld a,#16
3459 03be 42 mul x,a
3460 03bf 9f ld a,xl
3461 03c0 1a03 or a,(OFST+2,sp)
3462 03c2 6b01 ld (OFST+0,sp),a
3463 03c4 c65326 ld a,21286
3464 03c7 a40c and a,#12
3465 03c9 1a01 or a,(OFST+0,sp)
3466 03cb c75326 ld 21286,a
3467 ; 1042 if (TIM3_ICPolarity != TIM3_ICPOLARITY_RISING)
3469 03ce 0d02 tnz (OFST+1,sp)
3470 03d0 2706 jreq L3561
3471 ; 1044 TIM3->CCER1 |= TIM3_CCER1_CC2P;
3473 03d2 721a5327 bset 21287,#5
3475 03d6 2004 jra L5561
3476 03d8 L3561:
3477 ; 1048 TIM3->CCER1 &= (u8)(~TIM3_CCER1_CC2P);
3479 03d8 721b5327 bres 21287,#5
3480 03dc L5561:
3481 ; 1052 TIM3->CCER1 |= TIM3_CCER1_CC2E;
3483 03dc 72185327 bset 21287,#4
3484 ; 1054 }
3487 03e0 5b03 addw sp,#3
3488 03e2 81 ret
3501 xdef _TIM3_ClearITPendingBit
3502 xdef _TIM3_GetITStatus
3503 xdef _TIM3_ClearFlag
3504 xdef _TIM3_GetFlagStatus
3505 xdef _TIM3_GetPrescaler
3506 xdef _TIM3_GetCounter
3507 xdef _TIM3_GetCapture2
3508 xdef _TIM3_GetCapture1
3509 xdef _TIM3_SetIC2Prescaler
3510 xdef _TIM3_SetIC1Prescaler
3511 xdef _TIM3_SetCompare2
3512 xdef _TIM3_SetCompare1
3513 xdef _TIM3_SetAutoreload
3514 xdef _TIM3_SetCounter
3515 xdef _TIM3_SelectOCxM
3516 xdef _TIM3_CCxCmd
3517 xdef _TIM3_OC2PolarityConfig
3518 xdef _TIM3_OC1PolarityConfig
3519 xdef _TIM3_GenerateEvent
3520 xdef _TIM3_OC2PreloadConfig
3521 xdef _TIM3_OC1PreloadConfig
3522 xdef _TIM3_ARRPreloadConfig
3523 xdef _TIM3_ForcedOC2Config
3524 xdef _TIM3_ForcedOC1Config
3525 xdef _TIM3_PrescalerConfig
3526 xdef _TIM3_SelectOnePulseMode
3527 xdef _TIM3_UpdateRequestConfig
3528 xdef _TIM3_UpdateDisableConfig
3529 xdef _TIM3_ITConfig
3530 xdef _TIM3_Cmd
3531 xdef _TIM3_PWMIConfig
3532 xdef _TIM3_ICInit
3533 xdef _TIM3_OC2Init
3534 xdef _TIM3_OC1Init
3535 xdef _TIM3_TimeBaseInit
3536 xdef _TIM3_DeInit
3555 end
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