📄 stm8s_tim3.ls
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1015 011c cd0383 call L3_TI1_Config
1017 011f 84 pop a
1018 ; 246 TIM3_SetIC1Prescaler(TIM3_ICPrescaler);
1020 0120 7b08 ld a,(OFST+6,sp)
1021 0122 cd028c call _TIM3_SetIC1Prescaler
1023 ; 249 TI2_Config(icpolarity, icselection, TIM3_ICFilter);
1025 0125 7b09 ld a,(OFST+7,sp)
1026 0127 88 push a
1027 0128 7b03 ld a,(OFST+1,sp)
1028 012a 97 ld xl,a
1029 012b 7b02 ld a,(OFST+0,sp)
1030 012d 95 ld xh,a
1031 012e cd03b3 call L5_TI2_Config
1033 0131 84 pop a
1034 ; 252 TIM3_SetIC2Prescaler(TIM3_ICPrescaler);
1036 0132 7b08 ld a,(OFST+6,sp)
1037 0134 cd0299 call _TIM3_SetIC2Prescaler
1040 0137 2024 jra L724
1041 0139 L524:
1042 ; 257 TI2_Config((u8)TIM3_ICPolarity, (u8)TIM3_ICSelection,
1042 ; 258 (u8)TIM3_ICFilter);
1044 0139 7b09 ld a,(OFST+7,sp)
1045 013b 88 push a
1046 013c 7b08 ld a,(OFST+6,sp)
1047 013e 97 ld xl,a
1048 013f 7b05 ld a,(OFST+3,sp)
1049 0141 95 ld xh,a
1050 0142 cd03b3 call L5_TI2_Config
1052 0145 84 pop a
1053 ; 261 TIM3_SetIC2Prescaler(TIM3_ICPrescaler);
1055 0146 7b08 ld a,(OFST+6,sp)
1056 0148 cd0299 call _TIM3_SetIC2Prescaler
1058 ; 264 TI1_Config(icpolarity, icselection, TIM3_ICFilter);
1060 014b 7b09 ld a,(OFST+7,sp)
1061 014d 88 push a
1062 014e 7b03 ld a,(OFST+1,sp)
1063 0150 97 ld xl,a
1064 0151 7b02 ld a,(OFST+0,sp)
1065 0153 95 ld xh,a
1066 0154 cd0383 call L3_TI1_Config
1068 0157 84 pop a
1069 ; 267 TIM3_SetIC1Prescaler(TIM3_ICPrescaler);
1071 0158 7b08 ld a,(OFST+6,sp)
1072 015a cd028c call _TIM3_SetIC1Prescaler
1074 015d L724:
1075 ; 269 }
1078 015d 5b04 addw sp,#4
1079 015f 81 ret
1134 ; 278 void TIM3_Cmd(FunctionalState NewState)
1134 ; 279 {
1135 switch .text
1136 0160 _TIM3_Cmd:
1140 ; 281 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1142 ; 284 if (NewState != DISABLE)
1144 0160 4d tnz a
1145 0161 2706 jreq L754
1146 ; 286 TIM3->CR1 |= (u8)TIM3_CR1_CEN;
1148 0163 72105320 bset 21280,#0
1150 0167 2004 jra L164
1151 0169 L754:
1152 ; 290 TIM3->CR1 &= (u8)(~TIM3_CR1_CEN);
1154 0169 72115320 bres 21280,#0
1155 016d L164:
1156 ; 292 }
1159 016d 81 ret
1231 ; 307 void TIM3_ITConfig(TIM3_IT_TypeDef TIM3_IT, FunctionalState NewState)
1231 ; 308 {
1232 switch .text
1233 016e _TIM3_ITConfig:
1235 016e 89 pushw x
1236 00000000 OFST: set 0
1239 ; 310 assert_param(IS_TIM3_IT_OK(TIM3_IT));
1241 ; 311 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1243 ; 313 if (NewState != DISABLE)
1245 016f 9f ld a,xl
1246 0170 4d tnz a
1247 0171 2709 jreq L715
1248 ; 316 TIM3->IER |= (u8)TIM3_IT;
1250 0173 9e ld a,xh
1251 0174 ca5321 or a,21281
1252 0177 c75321 ld 21281,a
1254 017a 2009 jra L125
1255 017c L715:
1256 ; 321 TIM3->IER &= (u8)(~TIM3_IT);
1258 017c 7b01 ld a,(OFST+1,sp)
1259 017e 43 cpl a
1260 017f c45321 and a,21281
1261 0182 c75321 ld 21281,a
1262 0185 L125:
1263 ; 323 }
1266 0185 85 popw x
1267 0186 81 ret
1303 ; 332 void TIM3_UpdateDisableConfig(FunctionalState NewState)
1303 ; 333 {
1304 switch .text
1305 0187 _TIM3_UpdateDisableConfig:
1309 ; 335 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1311 ; 338 if (NewState != DISABLE)
1313 0187 4d tnz a
1314 0188 2706 jreq L145
1315 ; 340 TIM3->CR1 |= TIM3_CR1_UDIS;
1317 018a 72125320 bset 21280,#1
1319 018e 2004 jra L345
1320 0190 L145:
1321 ; 344 TIM3->CR1 &= (u8)(~TIM3_CR1_UDIS);
1323 0190 72135320 bres 21280,#1
1324 0194 L345:
1325 ; 346 }
1328 0194 81 ret
1386 ; 356 void TIM3_UpdateRequestConfig(TIM3_UpdateSource_TypeDef TIM3_UpdateSource)
1386 ; 357 {
1387 switch .text
1388 0195 _TIM3_UpdateRequestConfig:
1392 ; 359 assert_param(IS_TIM3_UPDATE_SOURCE_OK(TIM3_UpdateSource));
1394 ; 362 if (TIM3_UpdateSource != TIM3_UPDATESOURCE_GLOBAL)
1396 0195 4d tnz a
1397 0196 2706 jreq L375
1398 ; 364 TIM3->CR1 |= TIM3_CR1_URS;
1400 0198 72145320 bset 21280,#2
1402 019c 2004 jra L575
1403 019e L375:
1404 ; 368 TIM3->CR1 &= (u8)(~TIM3_CR1_URS);
1406 019e 72155320 bres 21280,#2
1407 01a2 L575:
1408 ; 370 }
1411 01a2 81 ret
1468 ; 381 void TIM3_SelectOnePulseMode(TIM3_OPMode_TypeDef TIM3_OPMode)
1468 ; 382 {
1469 switch .text
1470 01a3 _TIM3_SelectOnePulseMode:
1474 ; 384 assert_param(IS_TIM3_OPM_MODE_OK(TIM3_OPMode));
1476 ; 387 if (TIM3_OPMode != TIM3_OPMODE_REPETITIVE)
1478 01a3 4d tnz a
1479 01a4 2706 jreq L526
1480 ; 389 TIM3->CR1 |= TIM3_CR1_OPM;
1482 01a6 72165320 bset 21280,#3
1484 01aa 2004 jra L726
1485 01ac L526:
1486 ; 393 TIM3->CR1 &= (u8)(~TIM3_CR1_OPM);
1488 01ac 72175320 bres 21280,#3
1489 01b0 L726:
1490 ; 396 }
1493 01b0 81 ret
1561 ; 427 void TIM3_PrescalerConfig(TIM3_Prescaler_TypeDef Prescaler,
1561 ; 428 TIM3_PSCReloadMode_TypeDef TIM3_PSCReloadMode)
1561 ; 429 {
1562 switch .text
1563 01b1 _TIM3_PrescalerConfig:
1567 ; 431 assert_param(IS_TIM3_PRESCALER_RELOAD_OK(TIM3_PSCReloadMode));
1569 ; 432 assert_param(IS_TIM3_PRESCALER_OK(Prescaler));
1571 ; 435 TIM3->PSCR = (u8)Prescaler;
1573 01b1 9e ld a,xh
1574 01b2 c7532a ld 21290,a
1575 ; 438 TIM3->EGR = (u8)TIM3_PSCReloadMode;
1577 01b5 9f ld a,xl
1578 01b6 c75324 ld 21284,a
1579 ; 439 }
1582 01b9 81 ret
1640 ; 450 void TIM3_ForcedOC1Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
1640 ; 451 {
1641 switch .text
1642 01ba _TIM3_ForcedOC1Config:
1644 01ba 88 push a
1645 00000000 OFST: set 0
1648 ; 453 assert_param(IS_TIM3_FORCED_ACTION_OK(TIM3_ForcedAction));
1650 ; 456 TIM3->CCMR1 = (u8)((TIM3->CCMR1 & (u8)(~TIM3_CCMR_OCM)) | (u8)TIM3_ForcedAction);
1652 01bb c65325 ld a,21285
1653 01be a48f and a,#143
1654 01c0 1a01 or a,(OFST+1,sp)
1655 01c2 c75325 ld 21285,a
1656 ; 457 }
1659 01c5 84 pop a
1660 01c6 81 ret
1696 ; 468 void TIM3_ForcedOC2Config(TIM3_ForcedAction_TypeDef TIM3_ForcedAction)
1696 ; 469 {
1697 switch .text
1698 01c7 _TIM3_ForcedOC2Config:
1700 01c7 88 push a
1701 00000000 OFST: set 0
1704 ; 471 assert_param(IS_TIM3_FORCED_ACTION_OK(TIM3_ForcedAction));
1706 ; 474 TIM3->CCMR2 = (u8)((TIM3->CCMR2 & (u8)(~TIM3_CCMR_OCM)) | (u8)TIM3_ForcedAction);
1708 01c8 c65326 ld a,21286
1709 01cb a48f and a,#143
1710 01cd 1a01 or a,(OFST+1,sp)
1711 01cf c75326 ld 21286,a
1712 ; 475 }
1715 01d2 84 pop a
1716 01d3 81 ret
1752 ; 484 void TIM3_ARRPreloadConfig(FunctionalState NewState)
1752 ; 485 {
1753 switch .text
1754 01d4 _TIM3_ARRPreloadConfig:
1758 ; 487 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1760 ; 490 if (NewState != DISABLE)
1762 01d4 4d tnz a
1763 01d5 2706 jreq L547
1764 ; 492 TIM3->CR1 |= TIM3_CR1_ARPE;
1766 01d7 721e5320 bset 21280,#7
1768 01db 2004 jra L747
1769 01dd L547:
1770 ; 496 TIM3->CR1 &= (u8)(~TIM3_CR1_ARPE);
1772 01dd 721f5320 bres 21280,#7
1773 01e1 L747:
1774 ; 498 }
1777 01e1 81 ret
1813 ; 507 void TIM3_OC1PreloadConfig(FunctionalState NewState)
1813 ; 508 {
1814 switch .text
1815 01e2 _TIM3_OC1PreloadConfig:
1819 ; 510 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1821 ; 513 if (NewState != DISABLE)
1823 01e2 4d tnz a
1824 01e3 2706 jreq L767
1825 ; 515 TIM3->CCMR1 |= TIM3_CCMR_OCxPE;
1827 01e5 72165325 bset 21285,#3
1829 01e9 2004 jra L177
1830 01eb L767:
1831 ; 519 TIM3->CCMR1 &= (u8)(~TIM3_CCMR_OCxPE);
1833 01eb 72175325 bres 21285,#3
1834 01ef L177:
1835 ; 521 }
1838 01ef 81 ret
1874 ; 530 void TIM3_OC2PreloadConfig(FunctionalState NewState)
1874 ; 531 {
1875 switch .text
1876 01f0 _TIM3_OC2PreloadConfig:
1880 ; 533 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
1882 ; 536 if (NewState != DISABLE)
1884 01f0 4d tnz a
1885 01f1 2706 jreq L1101
1886 ; 538 TIM3->CCMR2 |= TIM3_CCMR_OCxPE;
1888 01f3 72165326 bset 21286,#3
1890 01f7 2004 jra L3101
1891 01f9 L1101:
1892 ; 542 TIM3->CCMR2 &= (u8)(~TIM3_CCMR_OCxPE);
1894 01f9 72175326 bres 21286,#3
1895 01fd L3101:
1896 ; 544 }
1899 01fd 81 ret
1964 ; 555 void TIM3_GenerateEvent(TIM3_EventSource_TypeDef TIM3_EventSource)
1964 ; 556 {
1965 switch .text
1966 01fe _TIM3_GenerateEvent:
1970 ; 558 assert_param(IS_TIM3_EVENT_SOURCE_OK(TIM3_EventSource));
1972 ; 561 TIM3->EGR = (u8)TIM3_EventSource;
1974 01fe c75324 ld 21284,a
1975 ; 562 }
1978 0201 81 ret
2014 ; 573 void TIM3_OC1PolarityConfig(TIM3_OCPolarity_TypeDef TIM3_OCPolarity)
2014 ; 574 {
2015 switch .text
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