📄 stm8s_tim1.ls
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3645 ; 1006 }
3648 0462 85 popw x
3649 0463 81 ret
3685 ; 1019 void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode)
3685 ; 1020 {
3686 switch .text
3687 0464 _TIM1_CounterModeConfig:
3689 0464 88 push a
3690 00000000 OFST: set 0
3693 ; 1022 assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));
3695 ; 1026 TIM1->CR1 = (u8)((TIM1->CR1 & (u8)((u8)(~TIM1_CR1_CMS) & (u8)(~TIM1_CR1_DIR))) | (u8)TIM1_CounterMode);
3697 0465 c65250 ld a,21072
3698 0468 a48f and a,#143
3699 046a 1a01 or a,(OFST+1,sp)
3700 046c c75250 ld 21072,a
3701 ; 1027 }
3704 046f 84 pop a
3705 0470 81 ret
3763 ; 1038 void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3763 ; 1039 {
3764 switch .text
3765 0471 _TIM1_ForcedOC1Config:
3767 0471 88 push a
3768 00000000 OFST: set 0
3771 ; 1041 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3773 ; 1044 TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3775 0472 c65258 ld a,21080
3776 0475 a48f and a,#143
3777 0477 1a01 or a,(OFST+1,sp)
3778 0479 c75258 ld 21080,a
3779 ; 1045 }
3782 047c 84 pop a
3783 047d 81 ret
3819 ; 1056 void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3819 ; 1057 {
3820 switch .text
3821 047e _TIM1_ForcedOC2Config:
3823 047e 88 push a
3824 00000000 OFST: set 0
3827 ; 1059 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3829 ; 1062 TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3831 047f c65259 ld a,21081
3832 0482 a48f and a,#143
3833 0484 1a01 or a,(OFST+1,sp)
3834 0486 c75259 ld 21081,a
3835 ; 1063 }
3838 0489 84 pop a
3839 048a 81 ret
3875 ; 1075 void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3875 ; 1076 {
3876 switch .text
3877 048b _TIM1_ForcedOC3Config:
3879 048b 88 push a
3880 00000000 OFST: set 0
3883 ; 1078 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3885 ; 1081 TIM1->CCMR3 = (u8)((TIM1->CCMR3 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3887 048c c6525a ld a,21082
3888 048f a48f and a,#143
3889 0491 1a01 or a,(OFST+1,sp)
3890 0493 c7525a ld 21082,a
3891 ; 1082 }
3894 0496 84 pop a
3895 0497 81 ret
3931 ; 1094 void TIM1_ForcedOC4Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
3931 ; 1095 {
3932 switch .text
3933 0498 _TIM1_ForcedOC4Config:
3935 0498 88 push a
3936 00000000 OFST: set 0
3939 ; 1097 assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
3941 ; 1100 TIM1->CCMR4 = (u8)((TIM1->CCMR4 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_ForcedAction);
3943 0499 c6525b ld a,21083
3944 049c a48f and a,#143
3945 049e 1a01 or a,(OFST+1,sp)
3946 04a0 c7525b ld 21083,a
3947 ; 1101 }
3950 04a3 84 pop a
3951 04a4 81 ret
3987 ; 1110 void TIM1_ARRPreloadConfig(FunctionalState NewState)
3987 ; 1111 {
3988 switch .text
3989 04a5 _TIM1_ARRPreloadConfig:
3993 ; 1113 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
3995 ; 1116 if (NewState != DISABLE)
3997 04a5 4d tnz a
3998 04a6 2706 jreq L5502
3999 ; 1118 TIM1->CR1 |= TIM1_CR1_ARPE;
4001 04a8 721e5250 bset 21072,#7
4003 04ac 2004 jra L7502
4004 04ae L5502:
4005 ; 1122 TIM1->CR1 &= (u8)(~TIM1_CR1_ARPE);
4007 04ae 721f5250 bres 21072,#7
4008 04b2 L7502:
4009 ; 1124 }
4012 04b2 81 ret
4047 ; 1133 void TIM1_SelectCOM(FunctionalState NewState)
4047 ; 1134 {
4048 switch .text
4049 04b3 _TIM1_SelectCOM:
4053 ; 1136 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4055 ; 1139 if (NewState != DISABLE)
4057 04b3 4d tnz a
4058 04b4 2706 jreq L7702
4059 ; 1141 TIM1->CR2 |= TIM1_CR2_COMS;
4061 04b6 72145251 bset 21073,#2
4063 04ba 2004 jra L1012
4064 04bc L7702:
4065 ; 1145 TIM1->CR2 &= (u8)(~TIM1_CR2_COMS);
4067 04bc 72155251 bres 21073,#2
4068 04c0 L1012:
4069 ; 1147 }
4072 04c0 81 ret
4108 ; 1155 void TIM1_CCPreloadControl(FunctionalState NewState)
4108 ; 1156 {
4109 switch .text
4110 04c1 _TIM1_CCPreloadControl:
4114 ; 1158 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4116 ; 1161 if (NewState != DISABLE)
4118 04c1 4d tnz a
4119 04c2 2706 jreq L1212
4120 ; 1163 TIM1->CR2 |= TIM1_CR2_CCPC;
4122 04c4 72105251 bset 21073,#0
4124 04c8 2004 jra L3212
4125 04ca L1212:
4126 ; 1167 TIM1->CR2 &= (u8)(~TIM1_CR2_CCPC);
4128 04ca 72115251 bres 21073,#0
4129 04ce L3212:
4130 ; 1169 }
4133 04ce 81 ret
4169 ; 1178 void TIM1_OC1PreloadConfig(FunctionalState NewState)
4169 ; 1179 {
4170 switch .text
4171 04cf _TIM1_OC1PreloadConfig:
4175 ; 1181 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4177 ; 1184 if (NewState != DISABLE)
4179 04cf 4d tnz a
4180 04d0 2706 jreq L3412
4181 ; 1186 TIM1->CCMR1 |= TIM1_CCMR_OCxPE;
4183 04d2 72165258 bset 21080,#3
4185 04d6 2004 jra L5412
4186 04d8 L3412:
4187 ; 1190 TIM1->CCMR1 &= (u8)(~TIM1_CCMR_OCxPE);
4189 04d8 72175258 bres 21080,#3
4190 04dc L5412:
4191 ; 1192 }
4194 04dc 81 ret
4230 ; 1201 void TIM1_OC2PreloadConfig(FunctionalState NewState)
4230 ; 1202 {
4231 switch .text
4232 04dd _TIM1_OC2PreloadConfig:
4236 ; 1204 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4238 ; 1207 if (NewState != DISABLE)
4240 04dd 4d tnz a
4241 04de 2706 jreq L5612
4242 ; 1209 TIM1->CCMR2 |= TIM1_CCMR_OCxPE;
4244 04e0 72165259 bset 21081,#3
4246 04e4 2004 jra L7612
4247 04e6 L5612:
4248 ; 1213 TIM1->CCMR2 &= (u8)(~TIM1_CCMR_OCxPE);
4250 04e6 72175259 bres 21081,#3
4251 04ea L7612:
4252 ; 1215 }
4255 04ea 81 ret
4291 ; 1224 void TIM1_OC3PreloadConfig(FunctionalState NewState)
4291 ; 1225 {
4292 switch .text
4293 04eb _TIM1_OC3PreloadConfig:
4297 ; 1227 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4299 ; 1230 if (NewState != DISABLE)
4301 04eb 4d tnz a
4302 04ec 2706 jreq L7022
4303 ; 1232 TIM1->CCMR3 |= TIM1_CCMR_OCxPE;
4305 04ee 7216525a bset 21082,#3
4307 04f2 2004 jra L1122
4308 04f4 L7022:
4309 ; 1236 TIM1->CCMR3 &= (u8)(~TIM1_CCMR_OCxPE);
4311 04f4 7217525a bres 21082,#3
4312 04f8 L1122:
4313 ; 1238 }
4316 04f8 81 ret
4352 ; 1248 void TIM1_OC4PreloadConfig(FunctionalState NewState)
4352 ; 1249 {
4353 switch .text
4354 04f9 _TIM1_OC4PreloadConfig:
4358 ; 1251 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4360 ; 1254 if (NewState != DISABLE)
4362 04f9 4d tnz a
4363 04fa 2706 jreq L1322
4364 ; 1256 TIM1->CCMR4 |= TIM1_CCMR_OCxPE;
4366 04fc 7216525b bset 21083,#3
4368 0500 2004 jra L3322
4369 0502 L1322:
4370 ; 1260 TIM1->CCMR4 &= (u8)(~TIM1_CCMR_OCxPE);
4372 0502 7217525b bres 21083,#3
4373 0506 L3322:
4374 ; 1262 }
4377 0506 81 ret
4412 ; 1270 void TIM1_OC1FastConfig(FunctionalState NewState)
4412 ; 1271 {
4413 switch .text
4414 0507 _TIM1_OC1FastConfig:
4418 ; 1273 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4420 ; 1276 if (NewState != DISABLE)
4422 0507 4d tnz a
4423 0508 2706 jreq L3522
4424 ; 1278 TIM1->CCMR1 |= TIM1_CCMR_OCxFE;
4426 050a 72145258 bset 21080,#2
4428 050e 2004 jra L5522
4429 0510 L3522:
4430 ; 1282 TIM1->CCMR1 &= (u8)(~TIM1_CCMR_OCxFE);
4432 0510 72155258 bres 21080,#2
4433 0514 L5522:
4434 ; 1284 }
4437 0514 81 ret
4472 ; 1294 void TIM1_OC2FastConfig(FunctionalState NewState)
4472 ; 1295 {
4473 switch .text
4474 0515 _TIM1_OC2FastConfig:
4478 ; 1297 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4480 ; 1300 if (NewState != DISABLE)
4482 0515 4d tnz a
4483 0516 2706 jreq L5722
4484 ; 1302 TIM1->CCMR2 |= TIM1_CCMR_OCxFE;
4486 0518 72145259 bset 21081,#2
4488 051c 2004 jra L7722
4489 051e L5722:
4490 ; 1306 TIM1->CCMR2 &= (u8)(~TIM1_CCMR_OCxFE);
4492 051e 72155259 bres 21081,#2
4493 0522 L7722:
4494 ; 1308 }
4497 0522 81 ret
4532 ; 1317 void TIM1_OC3FastConfig(FunctionalState NewState)
4532 ; 1318 {
4533 switch .text
4534 0523 _TIM1_OC3FastConfig:
4538 ; 1320 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
4540 ; 1323 if (NewState != DISABLE)
4542 0523 4d tnz a
4543 0524 2706 jreq L7132
4544 ; 1325 TIM1->CCMR3 |= TIM1_CCMR_OCxFE;
4546 0526 7214525a bset 21082,#2
4548 052a 2004 jra L1232
4549 052c L7132:
4550 ; 1329 TIM1->CCMR3 &= (u8)(~TIM1_CCMR_OCxFE);
4552 052c 7215525a bres 21082,#2
4553 0530 L1232:
4554 ; 1331⌨️ 快捷键说明
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