📄 stm8s_tim1.ls
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2586 036e 1a01 or a,(OFST+1,sp)
2587 0370 1a05 or a,(OFST+5,sp)
2588 0372 ca5253 or a,21075
2589 0375 c75253 ld 21075,a
2590 ; 694 }
2593 0378 85 popw x
2594 0379 81 ret
2683 ; 716 void TIM1_TIxExternalClockConfig(TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource,
2683 ; 717 TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
2683 ; 718 u8 ICFilter)
2683 ; 719 {
2684 switch .text
2685 037a _TIM1_TIxExternalClockConfig:
2687 037a 89 pushw x
2688 00000000 OFST: set 0
2691 ; 721 assert_param(IS_TIM1_TIXCLK_SOURCE_OK(TIM1_TIxExternalCLKSource));
2693 ; 722 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
2695 ; 723 assert_param(IS_TIM1_IC_FILTER_OK(ICFilter));
2697 ; 726 if (TIM1_TIxExternalCLKSource == TIM1_TIXEXTERNALCLK1SOURCE_TI2)
2699 037b 9e ld a,xh
2700 037c a160 cp a,#96
2701 037e 260f jrne L1131
2702 ; 728 TI2_Config((u8)TIM1_ICPolarity, (u8)TIM1_ICSELECTION_DIRECTTI, (u8)ICFilter);
2704 0380 7b05 ld a,(OFST+5,sp)
2705 0382 88 push a
2706 0383 ae0001 ldw x,#1
2707 0386 7b03 ld a,(OFST+3,sp)
2708 0388 95 ld xh,a
2709 0389 cd086c call L5_TI2_Config
2711 038c 84 pop a
2713 038d 200d jra L3131
2714 038f L1131:
2715 ; 732 TI1_Config((u8)TIM1_ICPolarity, (u8)TIM1_ICSELECTION_DIRECTTI, (u8)ICFilter);
2717 038f 7b05 ld a,(OFST+5,sp)
2718 0391 88 push a
2719 0392 ae0001 ldw x,#1
2720 0395 7b03 ld a,(OFST+3,sp)
2721 0397 95 ld xh,a
2722 0398 cd083c call L3_TI1_Config
2724 039b 84 pop a
2725 039c L3131:
2726 ; 736 TIM1_SelectInputTrigger(TIM1_TIxExternalCLKSource);
2728 039c 7b01 ld a,(OFST+1,sp)
2729 039e ad0a call _TIM1_SelectInputTrigger
2731 ; 739 TIM1->SMCR |= (u8)(TIM1_SLAVEMODE_EXTERNAL1);
2733 03a0 c65252 ld a,21074
2734 03a3 aa07 or a,#7
2735 03a5 c75252 ld 21074,a
2736 ; 740 }
2739 03a8 85 popw x
2740 03a9 81 ret
2825 ; 752 void TIM1_SelectInputTrigger(TIM1_TS_TypeDef TIM1_InputTriggerSource)
2825 ; 753 {
2826 switch .text
2827 03aa _TIM1_SelectInputTrigger:
2829 03aa 88 push a
2830 00000000 OFST: set 0
2833 ; 755 assert_param(IS_TIM1_TRIGGER_SELECTION_OK(TIM1_InputTriggerSource));
2835 ; 758 TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(~TIM1_SMCR_TS)) | (u8)TIM1_InputTriggerSource);
2837 03ab c65252 ld a,21074
2838 03ae a48f and a,#143
2839 03b0 1a01 or a,(OFST+1,sp)
2840 03b2 c75252 ld 21074,a
2841 ; 759 }
2844 03b5 84 pop a
2845 03b6 81 ret
2881 ; 769 void TIM1_UpdateDisableConfig(FunctionalState NewState)
2881 ; 770 {
2882 switch .text
2883 03b7 _TIM1_UpdateDisableConfig:
2887 ; 772 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
2889 ; 775 if (NewState != DISABLE)
2891 03b7 4d tnz a
2892 03b8 2706 jreq L1731
2893 ; 777 TIM1->CR1 |= TIM1_CR1_UDIS;
2895 03ba 72125250 bset 21072,#1
2897 03be 2004 jra L3731
2898 03c0 L1731:
2899 ; 781 TIM1->CR1 &= (u8)(~TIM1_CR1_UDIS);
2901 03c0 72135250 bres 21072,#1
2902 03c4 L3731:
2903 ; 783 }
2906 03c4 81 ret
2964 ; 793 void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
2964 ; 794 {
2965 switch .text
2966 03c5 _TIM1_UpdateRequestConfig:
2970 ; 796 assert_param(IS_TIM1_UPDATE_SOURCE_OK(TIM1_UpdateSource));
2972 ; 799 if (TIM1_UpdateSource != TIM1_UPDATESOURCE_GLOBAL)
2974 03c5 4d tnz a
2975 03c6 2706 jreq L3241
2976 ; 801 TIM1->CR1 |= TIM1_CR1_URS;
2978 03c8 72145250 bset 21072,#2
2980 03cc 2004 jra L5241
2981 03ce L3241:
2982 ; 805 TIM1->CR1 &= (u8)(~TIM1_CR1_URS);
2984 03ce 72155250 bres 21072,#2
2985 03d2 L5241:
2986 ; 807 }
2989 03d2 81 ret
3025 ; 816 void TIM1_SelectHallSensor(FunctionalState NewState)
3025 ; 817 {
3026 switch .text
3027 03d3 _TIM1_SelectHallSensor:
3031 ; 819 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
3033 ; 822 if (NewState != DISABLE)
3035 03d3 4d tnz a
3036 03d4 2706 jreq L5441
3037 ; 824 TIM1->CR2 |= TIM1_CR2_TI1S;
3039 03d6 721e5251 bset 21073,#7
3041 03da 2004 jra L7441
3042 03dc L5441:
3043 ; 828 TIM1->CR2 &= (u8)(~TIM1_CR2_TI1S);
3045 03dc 721f5251 bres 21073,#7
3046 03e0 L7441:
3047 ; 830 }
3050 03e0 81 ret
3107 ; 841 void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode)
3107 ; 842 {
3108 switch .text
3109 03e1 _TIM1_SelectOnePulseMode:
3113 ; 844 assert_param(IS_TIM1_OPM_MODE_OK(TIM1_OPMode));
3115 ; 847 if (TIM1_OPMode != TIM1_OPMODE_REPETITIVE)
3117 03e1 4d tnz a
3118 03e2 2706 jreq L7741
3119 ; 849 TIM1->CR1 |= TIM1_CR1_OPM;
3121 03e4 72165250 bset 21072,#3
3123 03e8 2004 jra L1051
3124 03ea L7741:
3125 ; 853 TIM1->CR1 &= (u8)(~TIM1_CR1_OPM);
3127 03ea 72175250 bres 21072,#3
3128 03ee L1051:
3129 ; 856 }
3132 03ee 81 ret
3230 ; 872 void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
3230 ; 873 {
3231 switch .text
3232 03ef _TIM1_SelectOutputTrigger:
3234 03ef 88 push a
3235 00000000 OFST: set 0
3238 ; 876 assert_param(IS_TIM1_TRGO_SOURCE_OK(TIM1_TRGOSource));
3240 ; 878 TIM1->CR2 = (u8)((TIM1->CR2 & (u8)(~TIM1_CR2_MMS )) | (u8) TIM1_TRGOSource);
3242 03f0 c65251 ld a,21073
3243 03f3 a48f and a,#143
3244 03f5 1a01 or a,(OFST+1,sp)
3245 03f7 c75251 ld 21073,a
3246 ; 879 }
3249 03fa 84 pop a
3250 03fb 81 ret
3324 ; 891 void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
3324 ; 892 {
3325 switch .text
3326 03fc _TIM1_SelectSlaveMode:
3328 03fc 88 push a
3329 00000000 OFST: set 0
3332 ; 895 assert_param(IS_TIM1_SLAVE_MODE_OK(TIM1_SlaveMode));
3334 ; 898 TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(~TIM1_SMCR_SMS)) | (u8)TIM1_SlaveMode);
3336 03fd c65252 ld a,21074
3337 0400 a4f8 and a,#248
3338 0402 1a01 or a,(OFST+1,sp)
3339 0404 c75252 ld 21074,a
3340 ; 900 }
3343 0407 84 pop a
3344 0408 81 ret
3380 ; 908 void TIM1_SelectMasterSlaveMode(FunctionalState NewState)
3380 ; 909 {
3381 switch .text
3382 0409 _TIM1_SelectMasterSlaveMode:
3386 ; 911 assert_param(IS_FUNCTIONALSTATE_OK(NewState));
3388 ; 914 if (NewState != DISABLE)
3390 0409 4d tnz a
3391 040a 2706 jreq L3161
3392 ; 916 TIM1->SMCR |= TIM1_SMCR_MSM;
3394 040c 721e5252 bset 21074,#7
3396 0410 2004 jra L5161
3397 0412 L3161:
3398 ; 920 TIM1->SMCR &= (u8)(~TIM1_SMCR_MSM);
3400 0412 721f5252 bres 21074,#7
3401 0416 L5161:
3402 ; 922 }
3405 0416 81 ret
3491 ; 944 void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode,
3491 ; 945 TIM1_ICPolarity_TypeDef TIM1_IC1Polarity,
3491 ; 946 TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
3491 ; 947 {
3492 switch .text
3493 0417 _TIM1_EncoderInterfaceConfig:
3495 0417 89 pushw x
3496 00000000 OFST: set 0
3499 ; 951 assert_param(IS_TIM1_ENCODER_MODE_OK(TIM1_EncoderMode));
3501 ; 952 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC1Polarity));
3503 ; 953 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC2Polarity));
3505 ; 956 if (TIM1_IC1Polarity != TIM1_ICPOLARITY_RISING)
3507 0418 9f ld a,xl
3508 0419 4d tnz a
3509 041a 2706 jreq L7561
3510 ; 958 TIM1->CCER1 |= TIM1_CCER1_CC1P;
3512 041c 7212525c bset 21084,#1
3514 0420 2004 jra L1661
3515 0422 L7561:
3516 ; 962 TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC1P);
3518 0422 7213525c bres 21084,#1
3519 0426 L1661:
3520 ; 965 if (TIM1_IC2Polarity != TIM1_ICPOLARITY_RISING)
3522 0426 0d05 tnz (OFST+5,sp)
3523 0428 2706 jreq L3661
3524 ; 967 TIM1->CCER1 |= TIM1_CCER1_CC2P;
3526 042a 721a525c bset 21084,#5
3528 042e 2004 jra L5661
3529 0430 L3661:
3530 ; 971 TIM1->CCER1 &= (u8)(~TIM1_CCER1_CC2P);
3532 0430 721b525c bres 21084,#5
3533 0434 L5661:
3534 ; 974 TIM1->SMCR = (u8)((TIM1->SMCR & (u8)(TIM1_SMCR_MSM | TIM1_SMCR_TS)) | (u8) TIM1_EncoderMode);
3536 0434 c65252 ld a,21074
3537 0437 a4f0 and a,#240
3538 0439 1a01 or a,(OFST+1,sp)
3539 043b c75252 ld 21074,a
3540 ; 977 TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_CCxS)) | (u8) CCMR_TIxDirect_Set);
3542 043e c65258 ld a,21080
3543 0441 a4fc and a,#252
3544 0443 aa01 or a,#1
3545 0445 c75258 ld 21080,a
3546 ; 978 TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_CCxS)) | (u8) CCMR_TIxDirect_Set);
3548 0448 c65259 ld a,21081
3549 044b a4fc and a,#252
3550 044d aa01 or a,#1
3551 044f c75259 ld 21081,a
3552 ; 980 }
3555 0452 85 popw x
3556 0453 81 ret
3623 ; 993 void TIM1_PrescalerConfig(u16 Prescaler,
3623 ; 994 TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
3623 ; 995 {
3624 switch .text
3625 0454 _TIM1_PrescalerConfig:
3627 0454 89 pushw x
3628 00000000 OFST: set 0
3631 ; 997 assert_param(IS_TIM1_PRESCALER_RELOAD_OK(TIM1_PSCReloadMode));
3633 ; 1000 TIM1->PSCRH = (u8)(Prescaler >> 8);
3635 0455 9e ld a,xh
3636 0456 c75260 ld 21088,a
3637 ; 1001 TIM1->PSCRL = (u8)(Prescaler);
3639 0459 9f ld a,xl
3640 045a c75261 ld 21089,a
3641 ; 1004 TIM1->EGR = (u8)TIM1_PSCReloadMode;
3643 045d 7b05 ld a,(OFST+5,sp)
3644 045f c75257 ld 21079,a
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