📄 stm8s_tim1.ls
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843 016c c75267 ld 21095,a
844 ; 224 TIM1->CCR2L = (u8)(TIM1_Pulse);
846 016f 7b0a ld a,(OFST+7,sp)
847 0171 c75268 ld 21096,a
848 ; 226 }
851 0174 5b05 addw sp,#5
852 0176 81 ret
956 ; 240 void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode,
956 ; 241 TIM1_OutputState_TypeDef TIM1_OutputState,
956 ; 242 TIM1_OutputNState_TypeDef TIM1_OutputNState,
956 ; 243 u16 TIM1_Pulse,
956 ; 244 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
956 ; 245 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
956 ; 246 TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
956 ; 247 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
956 ; 248 {
957 switch .text
958 0177 _TIM1_OC3Init:
960 0177 89 pushw x
961 0178 5203 subw sp,#3
962 00000003 OFST: set 3
965 ; 251 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
967 ; 252 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
969 ; 253 assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
971 ; 254 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
973 ; 255 assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
975 ; 256 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
977 ; 257 assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
979 ; 260 TIM1->CCER2 &= (u8)(~( TIM1_CCER2_CC3E | TIM1_CCER2_CC3NE | TIM1_CCER2_CC3P | TIM1_CCER2_CC3NP));
981 017a c6525d ld a,21085
982 017d a4f0 and a,#240
983 017f c7525d ld 21085,a
984 ; 262 TIM1->CCER2 |= (u8)((TIM1_OutputState & TIM1_CCER2_CC3E ) | (TIM1_OutputNState & TIM1_CCER2_CC3NE ) | (TIM1_OCPolarity & TIM1_CCER2_CC3P ) | (TIM1_OCNPolarity & TIM1_CCER2_CC3NP ));
986 0182 7b0c ld a,(OFST+9,sp)
987 0184 a408 and a,#8
988 0186 6b03 ld (OFST+0,sp),a
989 0188 7b0b ld a,(OFST+8,sp)
990 018a a402 and a,#2
991 018c 6b02 ld (OFST-1,sp),a
992 018e 7b08 ld a,(OFST+5,sp)
993 0190 a404 and a,#4
994 0192 6b01 ld (OFST-2,sp),a
995 0194 9f ld a,xl
996 0195 a401 and a,#1
997 0197 1a01 or a,(OFST-2,sp)
998 0199 1a02 or a,(OFST-1,sp)
999 019b 1a03 or a,(OFST+0,sp)
1000 019d ca525d or a,21085
1001 01a0 c7525d ld 21085,a
1002 ; 267 TIM1->CCMR3 = (u8)((TIM1->CCMR3 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode);
1004 01a3 c6525a ld a,21082
1005 01a6 a48f and a,#143
1006 01a8 1a04 or a,(OFST+1,sp)
1007 01aa c7525a ld 21082,a
1008 ; 270 TIM1->OISR &= (u8)(~(TIM1_OISR_OIS3 | TIM1_OISR_OIS3N));
1010 01ad c6526f ld a,21103
1011 01b0 a4cf and a,#207
1012 01b2 c7526f ld 21103,a
1013 ; 272 TIM1->OISR |= (u8)((TIM1_OISR_OIS3 & TIM1_OCIdleState) | (TIM1_OISR_OIS3N & TIM1_OCNIdleState));
1015 01b5 7b0e ld a,(OFST+11,sp)
1016 01b7 a420 and a,#32
1017 01b9 6b03 ld (OFST+0,sp),a
1018 01bb 7b0d ld a,(OFST+10,sp)
1019 01bd a410 and a,#16
1020 01bf 1a03 or a,(OFST+0,sp)
1021 01c1 ca526f or a,21103
1022 01c4 c7526f ld 21103,a
1023 ; 275 TIM1->CCR3H = (u8)(TIM1_Pulse >> 8);
1025 01c7 7b09 ld a,(OFST+6,sp)
1026 01c9 c75269 ld 21097,a
1027 ; 276 TIM1->CCR3L = (u8)(TIM1_Pulse);
1029 01cc 7b0a ld a,(OFST+7,sp)
1030 01ce c7526a ld 21098,a
1031 ; 278 }
1034 01d1 5b05 addw sp,#5
1035 01d3 81 ret
1109 ; 289 void TIM1_OC4Init(TIM1_OCMode_TypeDef TIM1_OCMode,
1109 ; 290 TIM1_OutputState_TypeDef TIM1_OutputState,
1109 ; 291 u16 TIM1_Pulse,
1109 ; 292 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
1109 ; 293 TIM1_OCIdleState_TypeDef TIM1_OCIdleState)
1109 ; 294 {
1110 switch .text
1111 01d4 _TIM1_OC4Init:
1113 01d4 89 pushw x
1114 01d5 88 push a
1115 00000001 OFST: set 1
1118 ; 297 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
1120 ; 298 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
1122 ; 299 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
1124 ; 300 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
1126 ; 305 TIM1->CCER2 &= (u8)(~(TIM1_CCER2_CC4E | TIM1_CCER2_CC4P));
1128 01d6 c6525d ld a,21085
1129 01d9 a4cf and a,#207
1130 01db c7525d ld 21085,a
1131 ; 307 TIM1->CCER2 |= (u8)((TIM1_OutputState & TIM1_CCER2_CC4E ) | (TIM1_OCPolarity & TIM1_CCER2_CC4P ));
1133 01de 7b08 ld a,(OFST+7,sp)
1134 01e0 a420 and a,#32
1135 01e2 6b01 ld (OFST+0,sp),a
1136 01e4 9f ld a,xl
1137 01e5 a410 and a,#16
1138 01e7 1a01 or a,(OFST+0,sp)
1139 01e9 ca525d or a,21085
1140 01ec c7525d ld 21085,a
1141 ; 310 TIM1->CCMR4 = (u8)((TIM1->CCMR4 & (u8)(~TIM1_CCMR_OCM)) | (TIM1_OCMode));
1143 01ef c6525b ld a,21083
1144 01f2 a48f and a,#143
1145 01f4 1a02 or a,(OFST+1,sp)
1146 01f6 c7525b ld 21083,a
1147 ; 313 if (TIM1_OCIdleState != TIM1_OCIDLESTATE_RESET)
1149 01f9 0d09 tnz (OFST+8,sp)
1150 01fb 270a jreq L534
1151 ; 315 TIM1->OISR |= (u8)(~TIM1_CCER2_CC4P);
1153 01fd c6526f ld a,21103
1154 0200 aadf or a,#223
1155 0202 c7526f ld 21103,a
1157 0205 2004 jra L734
1158 0207 L534:
1159 ; 319 TIM1->OISR &= (u8)(~TIM1_OISR_OIS4);
1161 0207 721d526f bres 21103,#6
1162 020b L734:
1163 ; 323 TIM1->CCR4H = (u8)(TIM1_Pulse >> 8);
1165 020b 7b06 ld a,(OFST+5,sp)
1166 020d c7526b ld 21099,a
1167 ; 324 TIM1->CCR4L = (u8)(TIM1_Pulse);
1169 0210 7b07 ld a,(OFST+6,sp)
1170 0212 c7526c ld 21100,a
1171 ; 326 }
1174 0215 5b03 addw sp,#3
1175 0217 81 ret
1380 ; 339 void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState,
1380 ; 340 TIM1_LockLevel_TypeDef TIM1_LockLevel,
1380 ; 341 u8 TIM1_DeadTime,
1380 ; 342 TIM1_BreakState_TypeDef TIM1_Break,
1380 ; 343 TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity,
1380 ; 344 TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
1380 ; 345 {
1381 switch .text
1382 0218 _TIM1_BDTRConfig:
1384 0218 89 pushw x
1385 00000000 OFST: set 0
1388 ; 349 assert_param(IS_TIM1_OSSI_STATE_OK(TIM1_OSSIState));
1390 ; 350 assert_param(IS_TIM1_LOCK_LEVEL_OK(TIM1_LockLevel));
1392 ; 351 assert_param(IS_TIM1_BREAK_STATE_OK(TIM1_Break));
1394 ; 352 assert_param(IS_TIM1_BREAK_POLARITY_OK(TIM1_BreakPolarity));
1396 ; 353 assert_param(IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(TIM1_AutomaticOutput));
1398 ; 356 TIM1->DTR = (u8)(TIM1_DeadTime);
1400 0219 7b05 ld a,(OFST+5,sp)
1401 021b c7526e ld 21102,a
1402 ; 360 TIM1->BKR = (u8)((u8)TIM1_OSSIState | \
1402 ; 361 (u8)TIM1_LockLevel | \
1402 ; 362 (u8)TIM1_Break | \
1402 ; 363 (u8)TIM1_BreakPolarity | \
1402 ; 364 (u8)TIM1_AutomaticOutput);
1404 021e 9f ld a,xl
1405 021f 1a01 or a,(OFST+1,sp)
1406 0221 1a06 or a,(OFST+6,sp)
1407 0223 1a07 or a,(OFST+7,sp)
1408 0225 1a08 or a,(OFST+8,sp)
1409 0227 c7526d ld 21101,a
1410 ; 366 }
1413 022a 85 popw x
1414 022b 81 ret
1616 ; 378 void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel,
1616 ; 379 TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
1616 ; 380 TIM1_ICSelection_TypeDef TIM1_ICSelection,
1616 ; 381 TIM1_ICPSC_TypeDef TIM1_ICPrescaler,
1616 ; 382 u8 TIM1_ICFilter)
1616 ; 383 {
1617 switch .text
1618 022c _TIM1_ICInit:
1620 022c 89 pushw x
1621 00000000 OFST: set 0
1624 ; 386 assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));
1626 ; 387 assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
1628 ; 388 assert_param(IS_TIM1_IC_SELECTION_OK(TIM1_ICSelection));
1630 ; 389 assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_ICPrescaler));
1632 ; 390 assert_param(IS_TIM1_IC_FILTER_OK(TIM1_ICFilter));
1634 ; 392 if (TIM1_Channel == TIM1_CHANNEL_1)
1636 022d 9e ld a,xh
1637 022e 4d tnz a
1638 022f 2614 jrne L766
1639 ; 395 TI1_Config((u8)TIM1_ICPolarity,
1639 ; 396 (u8)TIM1_ICSelection,
1639 ; 397 (u8)TIM1_ICFilter);
1641 0231 7b07 ld a,(OFST+7,sp)
1642 0233 88 push a
1643 0234 7b06 ld a,(OFST+6,sp)
1644 0236 97 ld xl,a
1645 0237 7b03 ld a,(OFST+3,sp)
1646 0239 95 ld xh,a
1647 023a cd083c call L3_TI1_Config
1649 023d 84 pop a
1650 ; 399 TIM1_SetIC1Prescaler(TIM1_ICPrescaler);
1652 023e 7b06 ld a,(OFST+6,sp)
1653 0240 cd06b8 call _TIM1_SetIC1Prescaler
1656 0243 2046 jra L176
1657 0245 L766:
1658 ; 401 else if (TIM1_Channel == TIM1_CHANNEL_2)
1660 0245 7b01 ld a,(OFST+1,sp)
1661 0247 a101 cp a,#1
1662 0249 2614 jrne L376
1663 ; 404 TI2_Config((u8)TIM1_ICPolarity,
1663 ; 405 (u8)TIM1_ICSelection,
1663 ; 406 (u8)TIM1_ICFilter);
1665 024b 7b07 ld a,(OFST+7,sp)
1666 024d 88 push a
1667 024e 7b06 ld a,(OFST+6,sp)
1668 0250 97 ld xl,a
1669 0251 7b03 ld a,(OFST+3,sp)
1670 0253 95 ld xh,a
1671 0254 cd086c call L5_TI2_Config
1673 0257 84 pop a
1674 ; 408 TIM1_SetIC2Prescaler(TIM1_ICPrescaler);
1676 0258 7b06 ld a,(OFST+6,sp)
1677 025a cd06c5 call _TIM1_SetIC2Prescaler
1680 025d 202c jra L176
1681 025f L376:
1682 ; 410 else if (TIM1_Channel == TIM1_CHANNEL_3)
1684 025f 7b01 ld a,(OFST+1,sp)
1685 0261 a102 cp a,#2
1686 0263 2614 jrne L776
1687 ; 413 TI3_Config((u8)TIM1_ICPolarity,
1687 ; 414 (u8)TIM1_ICSelection,
1687 ; 415 (u8)TIM1_ICFilter);
1689 0265 7b07 ld a,(OFST+7,sp)
1690 0267 88 push a
1691 0268 7b06 ld a,(OFST+6,sp)
1692 026a 97 ld xl,a
1693 026b 7b03 ld a,(OFST+3,sp)
1694 026d 95 ld xh,a
1695 026e cd089c call L7_TI3_Config
1697 0271 84 pop a
1698 ; 417 TIM1_SetIC3Prescaler(TIM1_ICPrescaler);
1700 0272 7b06 ld a,(OFST+6,sp)
1701 0274 cd06d2 call _TIM1_SetIC3Prescaler
1704 0277 2012 jra L176
1705 0279 L776:
1706 ; 422 TI4_Config((u8)TIM1_ICPolarity,
1706 ; 423 (u8)TIM1_ICSelection,
1706 ; 424 (u8)TIM1_ICFilter);
1708 0279 7b07 ld a,(OFST+7,sp)
1709 027b 88 push a
1710 027c 7b06 ld a,(OFST+6,sp)
1711 027e 97 ld xl,a
1712 027f 7b03 ld a,(OFST+3,sp)
1713 0281 95 ld xh,a
1714 0282 cd08cc call L11_TI4_Config
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