📄 stm8s_tim1.ls
字号:
1 ; C Compiler for STM8 (COSMIC Software)
2 ; Generator V4.2.8 - 03 Dec 2008
32 ; 50 void TIM1_DeInit(void)
32 ; 51 {
34 switch .text
35 0000 _TIM1_DeInit:
39 ; 52 TIM1->CR1 = TIM1_CR1_RESET_VALUE;
41 0000 725f5250 clr 21072
42 ; 53 TIM1->CR2 = TIM1_CR2_RESET_VALUE;
44 0004 725f5251 clr 21073
45 ; 54 TIM1->SMCR = TIM1_SMCR_RESET_VALUE;
47 0008 725f5252 clr 21074
48 ; 55 TIM1->ETR = TIM1_ETR_RESET_VALUE;
50 000c 725f5253 clr 21075
51 ; 56 TIM1->IER = TIM1_IER_RESET_VALUE;
53 0010 725f5254 clr 21076
54 ; 57 TIM1->SR2 = TIM1_SR2_RESET_VALUE;
56 0014 725f5256 clr 21078
57 ; 59 TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;
59 0018 725f525c clr 21084
60 ; 60 TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;
62 001c 725f525d clr 21085
63 ; 62 TIM1->CCMR1 = 0x01;
65 0020 35015258 mov 21080,#1
66 ; 63 TIM1->CCMR2 = 0x01;
68 0024 35015259 mov 21081,#1
69 ; 64 TIM1->CCMR3 = 0x01;
71 0028 3501525a mov 21082,#1
72 ; 65 TIM1->CCMR4 = 0x01;
74 002c 3501525b mov 21083,#1
75 ; 67 TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;
77 0030 725f525c clr 21084
78 ; 68 TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;
80 0034 725f525d clr 21085
81 ; 69 TIM1->CCMR1 = TIM1_CCMR1_RESET_VALUE;
83 0038 725f5258 clr 21080
84 ; 70 TIM1->CCMR2 = TIM1_CCMR2_RESET_VALUE;
86 003c 725f5259 clr 21081
87 ; 71 TIM1->CCMR3 = TIM1_CCMR3_RESET_VALUE;
89 0040 725f525a clr 21082
90 ; 72 TIM1->CCMR4 = TIM1_CCMR4_RESET_VALUE;
92 0044 725f525b clr 21083
93 ; 73 TIM1->CNTRH = TIM1_CNTRH_RESET_VALUE;
95 0048 725f525e clr 21086
96 ; 74 TIM1->CNTRL = TIM1_CNTRL_RESET_VALUE;
98 004c 725f525f clr 21087
99 ; 75 TIM1->PSCRH = TIM1_PSCRH_RESET_VALUE;
101 0050 725f5260 clr 21088
102 ; 76 TIM1->PSCRL = TIM1_PSCRL_RESET_VALUE;
104 0054 725f5261 clr 21089
105 ; 77 TIM1->ARRH = TIM1_ARRH_RESET_VALUE;
107 0058 35ff5262 mov 21090,#255
108 ; 78 TIM1->ARRL = TIM1_ARRL_RESET_VALUE;
110 005c 35ff5263 mov 21091,#255
111 ; 79 TIM1->CCR1H = TIM1_CCR1H_RESET_VALUE;
113 0060 725f5265 clr 21093
114 ; 80 TIM1->CCR1L = TIM1_CCR1L_RESET_VALUE;
116 0064 725f5266 clr 21094
117 ; 81 TIM1->CCR2H = TIM1_CCR2H_RESET_VALUE;
119 0068 725f5267 clr 21095
120 ; 82 TIM1->CCR2L = TIM1_CCR2L_RESET_VALUE;
122 006c 725f5268 clr 21096
123 ; 83 TIM1->CCR3H = TIM1_CCR3H_RESET_VALUE;
125 0070 725f5269 clr 21097
126 ; 84 TIM1->CCR3L = TIM1_CCR3L_RESET_VALUE;
128 0074 725f526a clr 21098
129 ; 85 TIM1->CCR4H = TIM1_CCR4H_RESET_VALUE;
131 0078 725f526b clr 21099
132 ; 86 TIM1->CCR4L = TIM1_CCR4L_RESET_VALUE;
134 007c 725f526c clr 21100
135 ; 87 TIM1->OISR = TIM1_OISR_RESET_VALUE;
137 0080 725f526f clr 21103
138 ; 88 TIM1->EGR = 0x01; /* TIM1_EGR_UG */
140 0084 35015257 mov 21079,#1
141 ; 89 TIM1->DTR = TIM1_DTR_RESET_VALUE;
143 0088 725f526e clr 21102
144 ; 90 TIM1->BKR = TIM1_BKR_RESET_VALUE;
146 008c 725f526d clr 21101
147 ; 91 TIM1->RCR = TIM1_RCR_RESET_VALUE;
149 0090 725f5264 clr 21092
150 ; 92 TIM1->SR1 = TIM1_SR1_RESET_VALUE;
152 0094 725f5255 clr 21077
153 ; 93 }
156 0098 81 ret
265 ; 103 void TIM1_TimeBaseInit(u16 TIM1_Prescaler,
265 ; 104 TIM1_CounterMode_TypeDef TIM1_CounterMode,
265 ; 105 u16 TIM1_Period,
265 ; 106 u8 TIM1_RepetitionCounter)
265 ; 107 {
266 switch .text
267 0099 _TIM1_TimeBaseInit:
269 0099 89 pushw x
270 00000000 OFST: set 0
273 ; 110 assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));
275 ; 113 TIM1->ARRH = (u8)(TIM1_Period >> 8);
277 009a 7b06 ld a,(OFST+6,sp)
278 009c c75262 ld 21090,a
279 ; 114 TIM1->ARRL = (u8)(TIM1_Period);
281 009f 7b07 ld a,(OFST+7,sp)
282 00a1 c75263 ld 21091,a
283 ; 117 TIM1->PSCRH = (u8)(TIM1_Prescaler >> 8);
285 00a4 9e ld a,xh
286 00a5 c75260 ld 21088,a
287 ; 118 TIM1->PSCRL = (u8)(TIM1_Prescaler);
289 00a8 9f ld a,xl
290 00a9 c75261 ld 21089,a
291 ; 121 TIM1->CR1 = (u8)(((TIM1->CR1) & (u8)(~(TIM1_CR1_CMS | TIM1_CR1_DIR))) | (u8)(TIM1_CounterMode));
293 00ac c65250 ld a,21072
294 00af a48f and a,#143
295 00b1 1a05 or a,(OFST+5,sp)
296 00b3 c75250 ld 21072,a
297 ; 124 TIM1->RCR = TIM1_RepetitionCounter;
299 00b6 7b08 ld a,(OFST+8,sp)
300 00b8 c75264 ld 21092,a
301 ; 126 }
304 00bb 85 popw x
305 00bc 81 ret
590 ; 140 void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode,
590 ; 141 TIM1_OutputState_TypeDef TIM1_OutputState,
590 ; 142 TIM1_OutputNState_TypeDef TIM1_OutputNState,
590 ; 143 u16 TIM1_Pulse,
590 ; 144 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
590 ; 145 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
590 ; 146 TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
590 ; 147 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
590 ; 148 {
591 switch .text
592 00bd _TIM1_OC1Init:
594 00bd 89 pushw x
595 00be 5203 subw sp,#3
596 00000003 OFST: set 3
599 ; 150 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
601 ; 151 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
603 ; 152 assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
605 ; 153 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
607 ; 154 assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
609 ; 155 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
611 ; 156 assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
613 ; 159 TIM1->CCER1 &= (u8)(~( TIM1_CCER1_CC1E | TIM1_CCER1_CC1NE | TIM1_CCER1_CC1P | TIM1_CCER1_CC1NP));
615 00c0 c6525c ld a,21084
616 00c3 a4f0 and a,#240
617 00c5 c7525c ld 21084,a
618 ; 161 TIM1->CCER1 |= (u8)((TIM1_OutputState & TIM1_CCER1_CC1E ) | (TIM1_OutputNState & TIM1_CCER1_CC1NE ) | (TIM1_OCPolarity & TIM1_CCER1_CC1P ) | (TIM1_OCNPolarity & TIM1_CCER1_CC1NP ));
620 00c8 7b0c ld a,(OFST+9,sp)
621 00ca a408 and a,#8
622 00cc 6b03 ld (OFST+0,sp),a
623 00ce 7b0b ld a,(OFST+8,sp)
624 00d0 a402 and a,#2
625 00d2 6b02 ld (OFST-1,sp),a
626 00d4 7b08 ld a,(OFST+5,sp)
627 00d6 a404 and a,#4
628 00d8 6b01 ld (OFST-2,sp),a
629 00da 9f ld a,xl
630 00db a401 and a,#1
631 00dd 1a01 or a,(OFST-2,sp)
632 00df 1a02 or a,(OFST-1,sp)
633 00e1 1a03 or a,(OFST+0,sp)
634 00e3 ca525c or a,21084
635 00e6 c7525c ld 21084,a
636 ; 164 TIM1->CCMR1 = (u8)((TIM1->CCMR1 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode);
638 00e9 c65258 ld a,21080
639 00ec a48f and a,#143
640 00ee 1a04 or a,(OFST+1,sp)
641 00f0 c75258 ld 21080,a
642 ; 167 TIM1->OISR &= (u8)(~(TIM1_OISR_OIS1 | TIM1_OISR_OIS1N));
644 00f3 c6526f ld a,21103
645 00f6 a4fc and a,#252
646 00f8 c7526f ld 21103,a
647 ; 169 TIM1->OISR |= (u8)(( TIM1_OCIdleState & TIM1_OISR_OIS1 ) | ( TIM1_OCNIdleState & TIM1_OISR_OIS1N ));
649 00fb 7b0e ld a,(OFST+11,sp)
650 00fd a402 and a,#2
651 00ff 6b03 ld (OFST+0,sp),a
652 0101 7b0d ld a,(OFST+10,sp)
653 0103 a401 and a,#1
654 0105 1a03 or a,(OFST+0,sp)
655 0107 ca526f or a,21103
656 010a c7526f ld 21103,a
657 ; 172 TIM1->CCR1H = (u8)(TIM1_Pulse >> 8);
659 010d 7b09 ld a,(OFST+6,sp)
660 010f c75265 ld 21093,a
661 ; 173 TIM1->CCR1L = (u8)(TIM1_Pulse);
663 0112 7b0a ld a,(OFST+7,sp)
664 0114 c75266 ld 21094,a
665 ; 174 }
668 0117 5b05 addw sp,#5
669 0119 81 ret
773 ; 188 void TIM1_OC2Init(TIM1_OCMode_TypeDef TIM1_OCMode,
773 ; 189 TIM1_OutputState_TypeDef TIM1_OutputState,
773 ; 190 TIM1_OutputNState_TypeDef TIM1_OutputNState,
773 ; 191 u16 TIM1_Pulse,
773 ; 192 TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
773 ; 193 TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
773 ; 194 TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
773 ; 195 TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
773 ; 196 {
774 switch .text
775 011a _TIM1_OC2Init:
777 011a 89 pushw x
778 011b 5203 subw sp,#3
779 00000003 OFST: set 3
782 ; 200 assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
784 ; 201 assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
786 ; 202 assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
788 ; 203 assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
790 ; 204 assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
792 ; 205 assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
794 ; 206 assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
796 ; 209 TIM1->CCER1 &= (u8)(~( TIM1_CCER1_CC2E | TIM1_CCER1_CC2NE | TIM1_CCER1_CC2P | TIM1_CCER1_CC2NP));
798 011d c6525c ld a,21084
799 0120 a40f and a,#15
800 0122 c7525c ld 21084,a
801 ; 211 TIM1->CCER1 |= (u8)((TIM1_OutputState & TIM1_CCER1_CC2E ) | (TIM1_OutputNState & TIM1_CCER1_CC2NE ) | (TIM1_OCPolarity & TIM1_CCER1_CC2P ) | (TIM1_OCNPolarity & TIM1_CCER1_CC2NP ));
803 0125 7b0c ld a,(OFST+9,sp)
804 0127 a480 and a,#128
805 0129 6b03 ld (OFST+0,sp),a
806 012b 7b0b ld a,(OFST+8,sp)
807 012d a420 and a,#32
808 012f 6b02 ld (OFST-1,sp),a
809 0131 7b08 ld a,(OFST+5,sp)
810 0133 a440 and a,#64
811 0135 6b01 ld (OFST-2,sp),a
812 0137 9f ld a,xl
813 0138 a410 and a,#16
814 013a 1a01 or a,(OFST-2,sp)
815 013c 1a02 or a,(OFST-1,sp)
816 013e 1a03 or a,(OFST+0,sp)
817 0140 ca525c or a,21084
818 0143 c7525c ld 21084,a
819 ; 215 TIM1->CCMR2 = (u8)((TIM1->CCMR2 & (u8)(~TIM1_CCMR_OCM)) | (u8)TIM1_OCMode);
821 0146 c65259 ld a,21081
822 0149 a48f and a,#143
823 014b 1a04 or a,(OFST+1,sp)
824 014d c75259 ld 21081,a
825 ; 218 TIM1->OISR &= (u8)(~(TIM1_OISR_OIS2 | TIM1_OISR_OIS2N));
827 0150 c6526f ld a,21103
828 0153 a4f3 and a,#243
829 0155 c7526f ld 21103,a
830 ; 220 TIM1->OISR |= (u8)((TIM1_OISR_OIS2 & TIM1_OCIdleState) | (TIM1_OISR_OIS2N & TIM1_OCNIdleState));
832 0158 7b0e ld a,(OFST+11,sp)
833 015a a408 and a,#8
834 015c 6b03 ld (OFST+0,sp),a
835 015e 7b0d ld a,(OFST+10,sp)
836 0160 a404 and a,#4
837 0162 1a03 or a,(OFST+0,sp)
838 0164 ca526f or a,21103
839 0167 c7526f ld 21103,a
840 ; 223 TIM1->CCR2H = (u8)(TIM1_Pulse >> 8);
842 016a 7b09 ld a,(OFST+6,sp)
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