📄 cpu_c.c
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*/
void CPU_IntSrcPrioSet (CPU_INT08U pos,
CPU_INT08U prio)
{
CPU_INT08U group;
CPU_INT08U nbr;
CPU_INT08U pos_max;
CPU_INT32U prio_32;
CPU_INT32U temp;
CPU_SR_ALLOC();
prio_32 = CPU_RevBits((CPU_INT08U)prio);
prio = (CPU_INT08U)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
switch (pos) {
case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
case CPU_INT_RSVD_07:
case CPU_INT_RSVD_08:
case CPU_INT_RSVD_09:
case CPU_INT_RSVD_10:
case CPU_INT_RSVD_13:
break;
/* ----------------- SYSTEM EXCEPTIONS ---------------- */
case CPU_INT_RESET: /* Reset (see Note #2). */
case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
break;
case CPU_INT_MEM: /* Memory management. */
CPU_CRITICAL_ENTER();
temp = CPU_REG_NVIC_SHPRI1;
temp &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
temp |= (prio << (0 * DEF_OCTET_NBR_BITS));
CPU_REG_NVIC_SHPRI1 = temp;
CPU_CRITICAL_EXIT();
break;
case CPU_INT_BUSFAULT: /* Bus fault. */
CPU_CRITICAL_ENTER();
temp = CPU_REG_NVIC_SHPRI1;
temp &= ~(DEF_OCTET_MASK << (1 * DEF_OCTET_NBR_BITS));
temp |= (prio << (1 * DEF_OCTET_NBR_BITS));
CPU_REG_NVIC_SHPRI1 = temp;
CPU_CRITICAL_EXIT();
break;
case CPU_INT_USAGEFAULT: /* Usage fault. */
CPU_CRITICAL_ENTER();
temp = CPU_REG_NVIC_SHPRI1;
temp &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
temp |= (prio << (2 * DEF_OCTET_NBR_BITS));
CPU_REG_NVIC_SHPRI1 = temp;
CPU_CRITICAL_EXIT();
break;
case CPU_INT_SVCALL: /* SVCall. */
CPU_CRITICAL_ENTER();
temp = CPU_REG_NVIC_SHPRI2;
temp &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
temp |= (prio << (3 * DEF_OCTET_NBR_BITS));
CPU_REG_NVIC_SHPRI2 = temp;
CPU_CRITICAL_EXIT();
break;
case CPU_INT_DBGMON: /* Debug monitor. */
CPU_CRITICAL_ENTER();
temp = CPU_REG_NVIC_SHPRI3;
temp &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
temp |= (prio << (0 * DEF_OCTET_NBR_BITS));
CPU_REG_NVIC_SHPRI3 = temp;
CPU_CRITICAL_EXIT();
break;
case CPU_INT_PENDSV: /* PendSV. */
CPU_CRITICAL_ENTER();
temp = CPU_REG_NVIC_SHPRI3;
temp &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
temp |= (prio << (2 * DEF_OCTET_NBR_BITS));
CPU_REG_NVIC_SHPRI3 = temp;
CPU_CRITICAL_EXIT();
break;
case CPU_INT_SYSTICK: /* SysTick. */
CPU_CRITICAL_ENTER();
temp = CPU_REG_NVIC_SHPRI3;
temp &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
temp |= (prio << (3 * DEF_OCTET_NBR_BITS));
CPU_REG_NVIC_SHPRI3 = temp;
CPU_CRITICAL_EXIT();
break;
/* ---------------- EXTERNAL INTERRUPT ---------------- */
default:
pos_max = CPU_INT_SRC_POS_MAX;
if (pos < pos_max) { /* See Note #3. */
group = (pos - 16) / 4;
nbr = (pos - 16) % 4;
CPU_CRITICAL_ENTER();
temp = CPU_REG_NVIC_PRIO(group);
temp &= ~(DEF_OCTET_MASK << (nbr * DEF_OCTET_NBR_BITS));
temp |= (prio << (nbr * DEF_OCTET_NBR_BITS));
CPU_REG_NVIC_PRIO(group) = temp;
CPU_CRITICAL_EXIT();
}
break;
}
}
/*$PAGE*/
/*
*********************************************************************************************************
* CPU_IntSrcPrioGet()
*
* Description : Get priority of an interrupt source.
*
* Argument(s) : pos Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
*
* Return(s) : Priority of interrupt source. If the interrupt source specified is invalid, then
* DEF_INT_16S_MIN_VAL is returned.
*
* Caller(s) : Application.
*
* Note(s) : (1) See 'CPU_IntSrcDis() Note #1'.
*
* (2) See 'CPU_IntSrcPrioSet() Note #2'.
*
* (3) See 'CPU_IntSrcDis() Note #3'.
*********************************************************************************************************
*/
CPU_INT16S CPU_IntSrcPrioGet (CPU_INT08U pos)
{
CPU_INT08U group;
CPU_INT08U nbr;
CPU_INT08U pos_max;
CPU_INT16S prio;
CPU_INT32U prio_32;
CPU_INT32U temp;
CPU_SR_ALLOC();
switch (pos) {
case CPU_INT_STK_PTR: /* ---------------- INVALID OR RESERVED --------------- */
case CPU_INT_RSVD_07:
case CPU_INT_RSVD_08:
case CPU_INT_RSVD_09:
case CPU_INT_RSVD_10:
case CPU_INT_RSVD_13:
prio = DEF_INT_16S_MIN_VAL;
break;
/* ----------------- SYSTEM EXCEPTIONS ---------------- */
case CPU_INT_RESET: /* Reset (see Note #2). */
prio = -3;
break;
case CPU_INT_NMI: /* Non-maskable interrupt (see Note #2). */
prio = -2;
break;
case CPU_INT_HFAULT: /* Hard fault (see Note #2). */
prio = -1;
break;
case CPU_INT_MEM: /* Memory management. */
CPU_CRITICAL_ENTER();
temp = CPU_REG_NVIC_SHPRI1;
prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
CPU_CRITICAL_EXIT();
break;
case CPU_INT_BUSFAULT: /* Bus fault. */
CPU_CRITICAL_ENTER();
temp = CPU_REG_NVIC_SHPRI1;
prio = (temp >> (1 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
CPU_CRITICAL_EXIT();
break;
case CPU_INT_USAGEFAULT: /* Usage fault. */
CPU_CRITICAL_ENTER();
temp = CPU_REG_NVIC_SHPRI1;
prio = (temp >> (2 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
break;
case CPU_INT_SVCALL: /* SVCall. */
CPU_CRITICAL_ENTER();
temp = CPU_REG_NVIC_SHPRI2;
prio = (temp >> (3 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
CPU_CRITICAL_EXIT();
break;
case CPU_INT_DBGMON: /* Debug monitor. */
CPU_CRITICAL_ENTER();
temp = CPU_REG_NVIC_SHPRI3;
prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
CPU_CRITICAL_EXIT();
break;
case CPU_INT_PENDSV: /* PendSV. */
CPU_CRITICAL_ENTER();
temp = CPU_REG_NVIC_SHPRI3;
prio = (temp >> (2 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
CPU_CRITICAL_EXIT();
break;
case CPU_INT_SYSTICK: /* SysTick. */
CPU_CRITICAL_ENTER();
temp = CPU_REG_NVIC_SHPRI3;
prio = (temp >> (3 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
CPU_CRITICAL_EXIT();
break;
/* ---------------- EXTERNAL INTERRUPT ---------------- */
default:
pos_max = CPU_INT_SRC_POS_MAX;
if (pos < pos_max) { /* See Note #3. */
group = (pos - 16) / 4;
nbr = (pos - 16) % 4;
CPU_CRITICAL_ENTER();
temp = CPU_REG_NVIC_PRIO(group);
CPU_CRITICAL_EXIT();
prio = (temp >> (nbr * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
} else {
prio = DEF_INT_16S_MIN_VAL;
}
break;
}
if (prio >= 0) {
prio_32 = CPU_RevBits((CPU_INT32U)prio);
prio = (CPU_INT16S)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
}
return (prio);
}
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