📄 lpc17xx.h
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typedef struct /* Common Registers */
{
__I uint32_t DMACIntStat;
__I uint32_t DMACIntTCStat;
__O uint32_t DMACIntTCClear;
__I uint32_t DMACIntErrStat;
__O uint32_t DMACIntErrClr;
__I uint32_t DMACRawIntTCStat;
__I uint32_t DMACRawIntErrStat;
__I uint32_t DMACEnbldChns;
__IO uint32_t DMACSoftBReq;
__IO uint32_t DMACSoftSReq;
__IO uint32_t DMACSoftLBReq;
__IO uint32_t DMACSoftLSReq;
__IO uint32_t DMACConfig;
__IO uint32_t DMACSync;
} GPDMA_TypeDef;
typedef struct /* Channel Registers */
{
__IO uint32_t DMACCSrcAddr;
__IO uint32_t DMACCDestAddr;
__IO uint32_t DMACCLLI;
__IO uint32_t DMACCControl;
__IO uint32_t DMACCConfig;
} GPDMACH_TypeDef;
/*------------- Universal Serial Bus (USB) -----------------------------------*/
typedef struct
{
__I uint32_t HcRevision; /* USB Host Registers */
__IO uint32_t HcControl;
__IO uint32_t HcCommandStatus;
__IO uint32_t HcInterruptStatus;
__IO uint32_t HcInterruptEnable;
__IO uint32_t HcInterruptDisable;
__IO uint32_t HcHCCA;
__I uint32_t HcPeriodCurrentED;
__IO uint32_t HcControlHeadED;
__IO uint32_t HcControlCurrentED;
__IO uint32_t HcBulkHeadED;
__IO uint32_t HcBulkCurrentED;
__I uint32_t HcDoneHead;
__IO uint32_t HcFmInterval;
__I uint32_t HcFmRemaining;
__I uint32_t HcFmNumber;
__IO uint32_t HcPeriodicStart;
__IO uint32_t HcLSTreshold;
__IO uint32_t HcRhDescriptorA;
__IO uint32_t HcRhDescriptorB;
__IO uint32_t HcRhStatus;
__IO uint32_t HcRhPortStatus1;
__IO uint32_t HcRhPortStatus2;
uint32_t RESERVED0[40];
__I uint32_t Module_ID;
__I uint32_t OTGIntSt; /* USB On-The-Go Registers */
__IO uint32_t OTGIntEn;
__O uint32_t OTGIntSet;
__O uint32_t OTGIntClr;
__IO uint32_t OTGStCtrl;
__IO uint32_t OTGTmr;
uint32_t RESERVED1[58];
__I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
__IO uint32_t USBDevIntEn;
__O uint32_t USBDevIntClr;
__O uint32_t USBDevIntSet;
__O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
__I uint32_t USBCmdData;
__I uint32_t USBRxData; /* USB Device Transfer Registers */
__O uint32_t USBTxData;
__I uint32_t USBRxPLen;
__O uint32_t USBTxPLen;
__IO uint32_t USBCtrl;
__O uint32_t USBDevIntPri;
__I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
__IO uint32_t USBEpIntEn;
__O uint32_t USBEpIntClr;
__O uint32_t USBEpIntSet;
__O uint32_t USBEpIntPri;
__IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
__O uint32_t USBEpInd;
__IO uint32_t USBMaxPSize;
__I uint32_t USBDMARSt; /* USB Device DMA Registers */
__O uint32_t USBDMARClr;
__O uint32_t USBDMARSet;
uint32_t RESERVED2[9];
__IO uint32_t USBUDCAH;
__I uint32_t USBEpDMASt;
__O uint32_t USBEpDMAEn;
__O uint32_t USBEpDMADis;
__I uint32_t USBDMAIntSt;
__IO uint32_t USBDMAIntEn;
uint32_t RESERVED3[2];
__I uint32_t USBEoTIntSt;
__O uint32_t USBEoTIntClr;
__O uint32_t USBEoTIntSet;
__I uint32_t USBNDDRIntSt;
__O uint32_t USBNDDRIntClr;
__O uint32_t USBNDDRIntSet;
__I uint32_t USBSysErrIntSt;
__O uint32_t USBSysErrIntClr;
__O uint32_t USBSysErrIntSet;
uint32_t RESERVED4[15];
__I uint32_t I2C_RX; /* USB OTG I2C Registers */
__O uint32_t I2C_WO;
__I uint32_t I2C_STS;
__IO uint32_t I2C_CTL;
__IO uint32_t I2C_CLKHI;
__O uint32_t I2C_CLKLO;
uint32_t RESERVED5[823];
union {
__IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
__IO uint32_t OTGClkCtrl;
};
union {
__I uint32_t USBClkSt;
__I uint32_t OTGClkSt;
};
} USB_TypeDef;
/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
typedef struct
{
__IO uint32_t MAC1; /* MAC Registers */
__IO uint32_t MAC2;
__IO uint32_t IPGT;
__IO uint32_t IPGR;
__IO uint32_t CLRT;
__IO uint32_t MAXF;
__IO uint32_t SUPP;
__IO uint32_t TEST;
__IO uint32_t MCFG;
__IO uint32_t MCMD;
__IO uint32_t MADR;
__O uint32_t MWTD;
__I uint32_t MRDD;
__I uint32_t MIND;
uint32_t RESERVED0[2];
__IO uint32_t SA0;
__IO uint32_t SA1;
__IO uint32_t SA2;
uint32_t RESERVED1[45];
__IO uint32_t Command; /* Control Registers */
__I uint32_t Status;
__IO uint32_t RxDescriptor;
__IO uint32_t RxStatus;
__IO uint32_t RxDescriptorNumber;
__I uint32_t RxProduceIndex;
__IO uint32_t RxConsumeIndex;
__IO uint32_t TxDescriptor;
__IO uint32_t TxStatus;
__IO uint32_t TxDescriptorNumber;
__IO uint32_t TxProduceIndex;
__I uint32_t TxConsumeIndex;
uint32_t RESERVED2[10];
__I uint32_t TSV0;
__I uint32_t TSV1;
__I uint32_t RSV;
uint32_t RESERVED3[3];
__IO uint32_t FlowControlCounter;
__I uint32_t FlowControlStatus;
uint32_t RESERVED4[34];
__IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
__IO uint32_t RxFilterWoLStatus;
__IO uint32_t RxFilterWoLClear;
uint32_t RESERVED5;
__IO uint32_t HashFilterL;
__IO uint32_t HashFilterH;
uint32_t RESERVED6[882];
__I uint32_t IntStatus; /* Module Control Registers */
__IO uint32_t IntEnable;
__O uint32_t IntClear;
__O uint32_t IntSet;
uint32_t RESERVED7;
__IO uint32_t PowerDown;
uint32_t RESERVED8;
__IO uint32_t Module_ID;
} EMAC_TypeDef;
#pragma no_anon_unions
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/* Base addresses */
#define FLASH_BASE (0x00000000UL)
#define RAM_BASE (0x10000000UL)
#define GPIO_BASE (0x2009C000UL)
#define APB0_BASE (0x40000000UL)
#define APB1_BASE (0x40080000UL)
#define AHB_BASE (0x50000000UL)
#define CM3_BASE (0xE0000000UL)
/* APB0 peripherals */
#define WDT_BASE (APB0_BASE + 0x00000)
#define TIM0_BASE (APB0_BASE + 0x04000)
#define TIM1_BASE (APB0_BASE + 0x08000)
#define UART0_BASE (APB0_BASE + 0x0C000)
#define UART1_BASE (APB0_BASE + 0x10000)
#define PWM1_BASE (APB0_BASE + 0x18000)
#define I2C0_BASE (APB0_BASE + 0x1C000)
#define SPI_BASE (APB0_BASE + 0x20000)
#define RTC_BASE (APB0_BASE + 0x24000)
#define GPIOINT_BASE (APB0_BASE + 0x28080)
#define PINCON_BASE (APB0_BASE + 0x2C000)
#define SSP1_BASE (APB0_BASE + 0x30000)
#define ADC_BASE (APB0_BASE + 0x34000)
#define CANAF_RAM_BASE (APB0_BASE + 0x38000)
#define CANAF_BASE (APB0_BASE + 0x3C000)
#define CANCR_BASE (APB0_BASE + 0x40000)
#define CAN1_BASE (APB0_BASE + 0x44000)
#define CAN2_BASE (APB0_BASE + 0x48000)
#define I2C1_BASE (APB0_BASE + 0x5C000)
/* APB1 peripherals */
#define SSP0_BASE (APB1_BASE + 0x08000)
#define DAC_BASE (APB1_BASE + 0x0C000)
#define TIM2_BASE (APB1_BASE + 0x10000)
#define TIM3_BASE (APB1_BASE + 0x14000)
#define UART2_BASE (APB1_BASE + 0x18000)
#define UART3_BASE (APB1_BASE + 0x1C000)
#define I2C2_BASE (APB1_BASE + 0x20000)
#define I2S_BASE (APB1_BASE + 0x28000)
#define RIT_BASE (APB1_BASE + 0x30000)
#define MCPWM_BASE (APB1_BASE + 0x38000)
#define QEI_BASE (APB1_BASE + 0x3C000)
#define SC_BASE (APB1_BASE + 0x7C000)
/* AHB peripherals */
#define EMAC_BASE (AHB_BASE + 0x00000)
#define GPDMA_BASE (AHB_BASE + 0x04000)
#define GPDMACH0_BASE (AHB_BASE + 0x04100)
#define GPDMACH1_BASE (AHB_BASE + 0x04120)
#define GPDMACH2_BASE (AHB_BASE + 0x04140)
#define GPDMACH3_BASE (AHB_BASE + 0x04160)
#define GPDMACH4_BASE (AHB_BASE + 0x04180)
#define GPDMACH5_BASE (AHB_BASE + 0x041A0)
#define GPDMACH6_BASE (AHB_BASE + 0x041C0)
#define GPDMACH7_BASE (AHB_BASE + 0x041E0)
#define USB_BASE (AHB_BASE + 0x0C000)
/* GPIOs */
#define GPIO0_BASE (GPIO_BASE + 0x00000)
#define GPIO1_BASE (GPIO_BASE + 0x00020)
#define GPIO2_BASE (GPIO_BASE + 0x00040)
#define GPIO3_BASE (GPIO_BASE + 0x00060)
#define GPIO4_BASE (GPIO_BASE + 0x00080)
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
#define SC (( SC_TypeDef *) SC_BASE)
#define GPIO0 (( GPIO_TypeDef *) GPIO0_BASE)
#define GPIO1 (( GPIO_TypeDef *) GPIO1_BASE)
#define GPIO2 (( GPIO_TypeDef *) GPIO2_BASE)
#define GPIO3 (( GPIO_TypeDef *) GPIO3_BASE)
#define GPIO4 (( GPIO_TypeDef *) GPIO4_BASE)
#define WDT (( WDT_TypeDef *) WDT_BASE)
#define TIM0 (( TIM_TypeDef *) TIM0_BASE)
#define TIM1 (( TIM_TypeDef *) TIM1_BASE)
#define TIM2 (( TIM_TypeDef *) TIM2_BASE)
#define TIM3 (( TIM_TypeDef *) TIM3_BASE)
#define RIT (( RIT_TypeDef *) RIT_BASE)
#define UART0 (( UART_TypeDef *) UART0_BASE)
#define UART1 (( UART1_TypeDef *) UART1_BASE)
#define UART2 (( UART_TypeDef *) UART2_BASE)
#define UART3 (( UART_TypeDef *) UART3_BASE)
#define PWM1 (( PWM_TypeDef *) PWM1_BASE)
#define I2C0 (( I2C_TypeDef *) I2C0_BASE)
#define I2C1 (( I2C_TypeDef *) I2C1_BASE)
#define I2C2 (( I2C_TypeDef *) I2C2_BASE)
#define I2S (( I2S_TypeDef *) I2S_BASE)
#define SPI (( SPI_TypeDef *) SPI_BASE)
#define RTC (( RTC_TypeDef *) RTC_BASE)
#define GPIOINT (( GPIOINT_TypeDef *) GPIOINT_BASE)
#define PINCON (( PINCON_TypeDef *) PINCON_BASE)
#define SSP0 (( SSP_TypeDef *) SSP0_BASE)
#define SSP1 (( SSP_TypeDef *) SSP1_BASE)
#define ADC (( ADC_TypeDef *) ADC_BASE)
#define DAC (( DAC_TypeDef *) DAC_BASE)
#define CANAF_RAM ((CANAF_RAM_TypeDef *) CANAF_RAM_BASE)
#define CANAF (( CANAF_TypeDef *) CANAF_BASE)
#define CANCR (( CANCR_TypeDef *) CANCR_BASE)
#define CAN1 (( CAN_TypeDef *) CAN1_BASE)
#define CAN2 (( CAN_TypeDef *) CAN2_BASE)
#define MCPWM (( MCPWM_TypeDef *) MCPWM_BASE)
#define QEI (( QEI_TypeDef *) QEI_BASE)
#define EMAC (( EMAC_TypeDef *) EMAC_BASE)
#define GPDMA (( GPDMA_TypeDef *) GPDMA_BASE)
#define GPDMACH0 (( GPDMACH_TypeDef *) GPDMACH0_BASE)
#define GPDMACH1 (( GPDMACH_TypeDef *) GPDMACH1_BASE)
#define GPDMACH2 (( GPDMACH_TypeDef *) GPDMACH2_BASE)
#define GPDMACH3 (( GPDMACH_TypeDef *) GPDMACH3_BASE)
#define GPDMACH4 (( GPDMACH_TypeDef *) GPDMACH4_BASE)
#define GPDMACH5 (( GPDMACH_TypeDef *) GPDMACH5_BASE)
#define GPDMACH6 (( GPDMACH_TypeDef *) GPDMACH6_BASE)
#define GPDMACH7 (( GPDMACH_TypeDef *) GPDMACH7_BASE)
#define USB (( USB_TypeDef *) USB_BASE)
#endif // __LPC17xx_H__
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