📄 os_cpu_a.lst
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ARM Macro Assembler Page 1
1 00000000 ;*******************************************************
*************************************************
2 00000000 ; uC/OS-II
3 00000000 ; The Real-Time
Kernel
4 00000000 ;
5 00000000 ; (c) Copyright 1992-2006,
Micrium, Weston, FL
6 00000000 ; All Rights Re
served
7 00000000 ;
8 00000000 ; ARM Cortex-M
3 Port
9 00000000 ;
10 00000000 ; File : OS_CPU_A.ASM
11 00000000 ; Version : V2.89
12 00000000 ; By : Jean J. Labrosse
13 00000000 ; Brian Nagel
14 00000000 ;
15 00000000 ; For : ARMv7M Cortex-M3
16 00000000 ; Mode : Thumb2
17 00000000 ; Toolchain : IAR EWARM
18 00000000 ;*******************************************************
*************************************************
19 00000000
20 00000000 ;*******************************************************
*************************************************
21 00000000 ; PUBLIC FUNCT
IONS
22 00000000 ;*******************************************************
*************************************************
23 00000000
24 00000000 EXTERN OSRunning ; External referenc
es
25 00000000 EXTERN OSPrioCur
26 00000000 EXTERN OSPrioHighRdy
27 00000000 EXTERN OSTCBCur
28 00000000 EXTERN OSTCBHighRdy
29 00000000 EXTERN OSIntExit
30 00000000 EXTERN OSTaskSwHook
31 00000000
32 00000000
33 00000000 EXPORT OS_CPU_SR_Save ; Functions decl
ared in this file
34 00000000 EXPORT OS_CPU_SR_Restore
35 00000000 EXPORT OSStartHighRdy
36 00000000 EXPORT OSCtxSw
37 00000000 EXPORT OSIntCtxSw
38 00000000 EXPORT PendSV_Handler
39 00000000 EXPORT IntDisAll
40 00000000 ; EXPORT OS_CPU_PendSVHandler
41 00000000
42 00000000
43 00000000 ;*******************************************************
*************************************************
44 00000000 ; EQUATES
45 00000000 ;*******************************************************
ARM Macro Assembler Page 2
*************************************************
46 00000000
47 00000000 E000ED04
NVIC_INT_CTRL
EQU 0xE000ED04 ; Interrupt control
state register.
48 00000000 E000ED22
NVIC_SYSPRI14
EQU 0xE000ED22 ; System priority r
egister (priority 1
4).
49 00000000 000000FF
NVIC_PENDSV_PRI
EQU 0xFF ; PendSV priority v
alue (lowest).
50 00000000 10000000
NVIC_PENDSVSET
EQU 0x10000000 ; Value to trigger
PendSV exception.
51 00000000
52 00000000 ;*******************************************************
*************************************************
53 00000000 ; CODE GENERATION D
IRECTIVES
54 00000000 ;*******************************************************
*************************************************
55 00000000 AREA OSKernelschedular,code,READONLY
56 00000000 THUMB
57 00000000
58 00000000 ;*******************************************************
*************************************************
59 00000000 ; CRITICAL SECTION MET
HOD 3 FUNCTIONS
60 00000000 ;
61 00000000 ; Description: Disable/Enable interrupts by preserving t
he state of interrupts. Generally speaking you
62 00000000 ; would store the state of the interrupt di
sable flag in the local variable 'cpu_sr' and then
63 00000000 ; disable interrupts. 'cpu_sr' is allocate
d in all of uC/OS-II's functions that need to
64 00000000 ; disable interrupts. You would restore th
e interrupt disable state by copying back 'cpu_sr'
65 00000000 ; into the CPU's status register.
66 00000000 ;
67 00000000 ; Prototypes : OS_CPU_SR OS_CPU_SR_Save(void);
68 00000000 ; void OS_CPU_SR_Restore(OS_CPU_S
R cpu_sr);
69 00000000 ;
70 00000000 ;
71 00000000 ; Note(s) : 1) These functions are used in general li
ke this:
72 00000000 ;
73 00000000 ; void Task (void *p_arg)
74 00000000 ; {
75 00000000 ; #if OS_CRITICAL_METHOD == 3 /
* Allocate storage for CPU status register */
76 00000000 ; OS_CPU_SR cpu_sr;
77 00000000 ; #endif
78 00000000 ;
ARM Macro Assembler Page 3
79 00000000 ; :
80 00000000 ; :
81 00000000 ; OS_ENTER_CRITICAL(); /
* cpu_sr = OS_CPU_SaveSR(); */
82 00000000 ; :
83 00000000 ; :
84 00000000 ; OS_EXIT_CRITICAL(); /
* OS_CPU_RestoreSR(cpu_sr); */
85 00000000 ; :
86 00000000 ; :
87 00000000 ; }
88 00000000 ;*******************************************************
*************************************************
89 00000000
90 00000000 OS_CPU_SR_Save
91 00000000 F3EF 8010 MRS R0, PRIMASK ; Set prio int mask
to mask all (excep
t faults)
92 00000004 B672 CPSID I
93 00000006 4770 BX LR
94 00000008
95 00000008 OS_CPU_SR_Restore
96 00000008 F380 8810 MSR PRIMASK, R0
97 0000000C 4770 BX LR
98 0000000E
99 0000000E ;*******************************************************
*************************************************
100 0000000E ; START MULTITA
SKING
101 0000000E ; void OSStartHigh
Rdy(void)
102 0000000E ;
103 0000000E ; Note(s) : 1) This function triggers a PendSV exception
(essentially, causes a context switch) to cause
104 0000000E ; the first task to start.
105 0000000E ;
106 0000000E ; 2) OSStartHighRdy() MUST:
107 0000000E ; a) Setup PendSV exception priority to low
est;
108 0000000E ; b) Set initial PSP to 0, to tell context
switcher this is first run;
109 0000000E ; c) Set OSRunning to TRUE;
110 0000000E ; d) Trigger PendSV exception;
111 0000000E ; e) Enable interrupts (tasks will run with
interrupts enabled).
112 0000000E ;*******************************************************
*************************************************
113 0000000E
114 0000000E OSStartHighRdy
115 0000000E 481D LDR R0, =NVIC_SYSPRI14 ; Set the Pe
ndSV exception prio
rity
116 00000010 F04F 01FF LDR R1, =NVIC_PENDSV_PRI
117 00000014 7001 STRB R1, [R0]
118 00000016
119 00000016 2000 MOVS R0, #0 ; Set the PSP to 0
for initial context
switch call
120 00000018 F380 8809 MSR PSP, R0
ARM Macro Assembler Page 4
121 0000001C
122 0000001C 481A LDR R0, =OSRunning
; OSRunning = TRUE
123 0000001E 2101 MOVS R1, #1
124 00000020 7001 STRB R1, [R0]
125 00000022
126 00000022 481A LDR R0, =NVIC_INT_CTRL ; Trigger th
e PendSV exception
(causes context swi
tch)
127 00000024 F04F 5180 LDR R1, =NVIC_PENDSVSET
128 00000028 6001 STR R1, [R0]
129 0000002A
130 0000002A B662 CPSIE I ; Enable interrupts
at processor level
131 0000002C
132 0000002C OSStartHang
133 0000002C E7FE B OSStartHang ; Should never get
here
134 0000002E
135 0000002E
136 0000002E ;*******************************************************
*************************************************
137 0000002E ; PERFORM A CONTEXT SWITCH
(From task level)
138 0000002E ; void OSCtxSw
(void)
139 0000002E ;
140 0000002E ; Note(s) : 1) OSCtxSw() is called when OS wants to perf
orm a task context switch. This function
141 0000002E ; triggers the PendSV exception which is wh
ere the real work is done.
142 0000002E ;*******************************************************
*************************************************
143 0000002E
144 0000002E OSCtxSw
145 0000002E 4817 LDR R0, =NVIC_INT_CTRL ; Trigger th
e PendSV exception
(causes context swi
tch)
146 00000030 F04F 5180 LDR R1, =NVIC_PENDSVSET
147 00000034 6001 STR R1, [R0]
148 00000036 4770 BX LR
149 00000038
150 00000038 ;*******************************************************
*************************************************
151 00000038 ; PERFORM A CONTEXT SWITCH (
From interrupt level)
152 00000038 ; void OSIntCtxS
w(void)
153 00000038 ;
154 00000038 ; Notes: 1) OSIntCtxSw() is called by OSIntExit() whe
n it determines a context switch is needed as
155 00000038 ; the result of an interrupt. This functio
n simply triggers a PendSV exception which will
156 00000038 ; be handled when there are no more interru
pts active and interrupts are enabled.
157 00000038 ;*******************************************************
ARM Macro Assembler Page 5
*************************************************
158 00000038
159 00000038 OSIntCtxSw
160 00000038 4814 LDR R0, =NVIC_INT_CTRL ; Trigger th
e PendSV exception
(causes context swi
tch)
161 0000003A F04F 5180 LDR R1, =NVIC_PENDSVSET
162 0000003E 6001 STR R1, [R0]
163 00000040 4770 BX LR
164 00000042
165 00000042 ;*******************************************************
*************************************************
166 00000042 ; HANDLE PendSV
EXCEPTION
167 00000042 ; void OS_CPU_PendSV
Handler(void)
168 00000042 ;
169 00000042 ; Note(s) : 1) PendSV is used to cause a context switch.
This is a recommended method for performing
170 00000042 ; context switches with Cortex-M3. This is
because the Cortex-M3 auto-saves half of the
171 00000042 ; processor context on any exception, and r
estores same on return from exception. So only
172 00000042 ; saving of R4-R11 is required and fixing u
p the stack pointers. Using the PendSV exception
173 00000042 ; this way means that context saving and re
storing is identical whether it is initiated from
174 00000042 ; a thread or occurs due to an interrupt or
exception.
175 00000042 ;
176 00000042 ; 2) Pseudo-code is:
177 00000042 ; a) Get the process SP, if 0 then skip (go
to d) the saving part (first context switch);
178 00000042 ; b) Save remaining regs r4-r11 on process
stack;
179 00000042 ; c) Save the process SP in its TCB, OSTCBC
ur->OSTCBStkPtr = SP;
180 00000042 ; d) Call OSTaskSwHook();
181 00000042 ; e) Get current high priority, OSPrioCur =
OSPrioHighRdy;
182 00000042 ; f) Get current ready thread TCB, OSTCBCur
= OSTCBHighRdy;
183 00000042 ; g) Get new process SP from TCB, SP = OSTC
BHighRdy->OSTCBStkPtr;
184 00000042 ; h) Restore R4-R11 from new process stack;
185 00000042 ; i) Perform exception return which will re
store remaining context.
186 00000042 ;
187 00000042 ; 3) On entry into PendSV handler:
188 00000042 ; a) The following have been saved on the p
rocess stack (by processor):
189 00000042 ; xPSR, PC, LR, R12, R0-R3
190 00000042 ; b) Processor mode is switched to Handler
mode (from Thread mode)
191 00000042 ; c) Stack is Main stack (switched from Pro
cess stack)
192 00000042 ; d) OSTCBCur points to the OS_TCB of
ARM Macro Assembler Page 6
the task to suspend
193 00000042 ; OSTCBHighRdy points to the OS_TCB of
the task to resume
194 00000042 ;
195 00000042 ; 4) Since PendSV is set to lowest priority in
the system (by OSStartHighRdy() above), we
196 00000042 ; know that it will only be run when no oth
er exception or interrupt is active, and
197 00000042 ; therefore safe to assume that context bei
ng switched out was using the process stack (PSP).
198 00000042 ;*******************************************************
*************************************************
199 00000042
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