lpc17xx_emac.h.svn-base

uCOSII_lwip_lpc1768

#define EMAC_PHY_SR_JABBER					(1<<5)		/**< Jabber detect */
#define EMAC_PHY_SR_AUTO_DONE				(1<<4)		/**< Auto Negotiation complete */
#define EMAC_PHY_SR_LOOPBACK				(1<<3)		/**< Loop back status */
#define EMAC_PHY_SR_DUP						(1<<2)		/**< Duplex status */
#define EMAC_PHY_SR_SPEED					(1<<1)		/**< Speed status */
#define EMAC_PHY_SR_LINK					(1<<0)		/**< Link Status */

#define EMAC_PHY_FULLD_100M      0x2100      /**< Full Duplex 100Mbit               */
#define EMAC_PHY_HALFD_100M      0x2000      /**< Half Duplex 100Mbit               */
#define EMAC_PHY_FULLD_10M       0x0100      /**< Full Duplex 10Mbit                */
#define EMAC_PHY_HALFD_10M       0x0000      /**< Half Duplex 10MBit                */
#define EMAC_PHY_AUTO_NEG        0x3000      /**< Select Auto Negotiation           */

#define EMAC_DEF_ADR    0x0100      /**< Default PHY device address        */
#define EMAC_DP83848C_ID         0x20005C90  /**< PHY Identifier                    */

#define EMAC_PHY_SR_100_SPEED		((1<<14)|(1<<13))
#define EMAC_PHY_SR_FULL_DUP		((1<<14)|(1<<12))
#define EMAC_PHY_BMSR_LINK_STATUS			(1<<2)		/**< Link status */

#elif defined(IAR_LPC_1768)
/* KSZ8721BL PHY definition ------------------------------------------------------------ */
/** PHY device reset time out definition */
#define EMAC_PHY_RESP_TOUT		0x100000UL

/* ENET Device Revision ID */
#define EMAC_OLD_EMAC_MODULE_ID  0x39022000  /**< Rev. ID for first rev '-'         */

/*********************************************************************//**
 * Macro defines for KSZ8721BL PHY Registers
 **********************************************************************/
#define EMAC_PHY_REG_BMCR        0x00        /**< Basic Mode Control Register       */
#define EMAC_PHY_REG_BMSR        0x01        /**< Basic Mode Status Register        */
#define EMAC_PHY_REG_IDR1        0x02        /**< PHY Identifier 1                  */
#define EMAC_PHY_REG_IDR2        0x03        /**< PHY Identifier 2                  */
#define EMAC_PHY_REG_ANAR        0x04        /**< Auto-Negotiation Advertisement    */
#define EMAC_PHY_REG_ANLPAR      0x05        /**< Auto-Neg. Link Partner Abitily    */
#define EMAC_PHY_REG_ANER        0x06        /**< Auto-Neg. Expansion Register      */
#define EMAC_PHY_REG_ANNPTR      0x07        /**< Auto-Neg. Next Page TX            */
#define EMAC_PHY_REG_LPNPA		 0x08		 /**< Link Partner Next Page Ability    */
#define EMAC_PHY_REG_REC		 0x15		 /**< RXError Counter Register			*/
#define EMAC_PHY_REG_ISC		 0x1b		 /**< Interrupt Control/Status Register */
#define EMAC_PHY_REG_100BASE	 0x1f		 /**< 100BASE-TX PHY Control Register   */

/*********************************************************************//**
 * Macro defines for PHY Basic Mode Control Register
 **********************************************************************/
#define EMAC_PHY_BMCR_RESET     			(1<<15)		/**< Reset bit */
#define EMAC_PHY_BMCR_LOOPBACK      		(1<<14)		/**< Loop back */
#define EMAC_PHY_BMCR_SPEED_SEL     		(1<<13)		/**< Speed selection */
#define EMAC_PHY_BMCR_AN					(1<<12)		/**< Auto Negotiation */
#define EMAC_PHY_BMCR_POWERDOWN				(1<<11)		/**< Power down mode */
#define EMAC_PHY_BMCR_ISOLATE				(1<<10)		/**< Isolate */
#define EMAC_PHY_BMCR_RE_AN					(1<<9)		/**< Restart auto negotiation */
#define EMAC_PHY_BMCR_DUPLEX				(1<<8)		/**< Duplex mode */
#define EMAC_PHY_BMCR_COLLISION				(1<<7)		/**< Collision test */
#define EMAC_PHY_BMCR_TXDIS					(1<<0)		/**< Disable transmit */

/*********************************************************************//**
 * Macro defines for PHY Basic Mode Status Register
 **********************************************************************/
#define EMAC_PHY_BMSR_100BE_T4        	   	(1<<15)		/**< 100 base T4 */
#define EMAC_PHY_BMSR_100TX_FULL			(1<<14)		/**< 100 base full duplex */
#define EMAC_PHY_BMSR_100TX_HALF			(1<<13)		/**< 100 base half duplex */
#define EMAC_PHY_BMSR_10BE_FULL				(1<<12)		/**< 10 base T full duplex */
#define EMAC_PHY_BMSR_10BE_HALF				(1<<11)		/**< 10 base T half duplex */
#define EMAC_PHY_BMSR_NOPREAM				(1<<6)		/**< MF Preamable Supress */
#define EMAC_PHY_BMSR_AUTO_DONE				(1<<5)		/**< Auto negotiation complete */
#define EMAC_PHY_BMSR_REMOTE_FAULT			(1<<4)		/**< Remote fault */
#define EMAC_PHY_BMSR_NO_AUTO				(1<<3)		/**< Auto Negotiation ability */
#define EMAC_PHY_BMSR_LINK_STATUS			(1<<2)		/**< Link status */
#define EMAC_PHY_BMSR_JABBER_DETECT			(1<<1)		/**< Jabber detect */
#define EMAC_PHY_BMSR_EXTEND				(1<<0)		/**< Extended support */

/*********************************************************************//**
 * Macro defines for PHY Identifier
 **********************************************************************/
/* PHY Identifier 1 bitmap definitions */
#define EMAC_PHY_IDR1(n)		(n & 0xFFFF)		/**< PHY ID1 Number */

/* PHY Identifier 2 bitmap definitions */
#define EMAC_PHY_IDR2(n)		(n & 0xFFFF)		/**< PHY ID2 Number */

/*********************************************************************//**
 * Macro defines for Auto-Negotiation Advertisement
 **********************************************************************/
#define EMAC_PHY_AN_NEXTPAGE					(1<<15)		/**<  Next page capable */
#define EMAC_PHY_AN_REMOTE_FAULT				(1<<13)		/**< Remote Fault support */
#define EMAC_PHY_AN_PAUSE						(1<<10)		/**< Pause support */
#define EMAC_PHY_AN_100BASE_T4					(1<<9)		/**< T4 capable */
#define EMAC_PHY_AN_100BASE_TX_FD				(1<<8)		/**< TX with Full-duplex capable */
#define EMAC_PHY_AN_100BASE_TX					(1<<7)		/**< TX capable */
#define EMAC_PHY_AN_10BASE_T_FD					(1<<6)		/**< 10Mbps with full-duplex capable */
#define EMAC_PHY_AN_10BASE_T					(1<<5)		/**< 10Mbps capable */
#define EMAC_PHY_AN_FIELD(n)					(n & 0x1F)  /**< Selector Field */

#define EMAC_PHY_FULLD_100M      0x2100      /**< Full Duplex 100Mbit               */
#define EMAC_PHY_HALFD_100M      0x2000      /**< Half Duplex 100Mbit               */
#define EMAC_PHY_FULLD_10M       0x0100      /**< Full Duplex 10Mbit                */
#define EMAC_PHY_HALFD_10M       0x0000      /**< Half Duplex 10MBit                */
#define EMAC_PHY_AUTO_NEG        0x3000      /**< Select Auto Negotiation           */

#define EMAC_PHY_SR_100_SPEED		((1<<14)|(1<<13))
#define EMAC_PHY_SR_FULL_DUP		((1<<14)|(1<<12))

#define EMAC_DEF_ADR    (0x01<<8)		/**< Default PHY device address        */
#define EMAC_KSZ8721BL_ID 	((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
#endif

/**
 * @}
 */


/* Public Types --------------------------------------------------------------- */
/** @defgroup EMAC_Public_Types EMAC Public Types
 * @{
 */

/* Descriptor and status formats ---------------------------------------------- */

/**
 * @brief RX Descriptor structure type definition
 */
typedef struct {
	uint32_t Packet;	/**< Receive Packet Descriptor */
	uint32_t Ctrl;		/**< Receive Control Descriptor */
} RX_Desc;

/**
 * @brief RX Status structure type definition
 */
typedef struct {
	uint32_t Info;		/**< Receive Information Status */
	uint32_t HashCRC;	/**< Receive Hash CRC Status */
} RX_Stat;

/**
 * @brief TX Descriptor structure type definition
 */
typedef struct {
	uint32_t Packet;	/**< Transmit Packet Descriptor */
	uint32_t Ctrl;		/**< Transmit Control Descriptor */
} TX_Desc;

/**
 * @brief TX Status structure type definition
 */
typedef struct {
   uint32_t Info;		/**< Transmit Information Status */
} TX_Stat;


/**
 * @brief TX Data Buffer structure definition
 */
typedef struct {
	uint32_t ulDataLen;			/**< Data length */
	uint32_t *pbDataBuf;		/**< A word-align data pointer to data buffer */
} EMAC_PACKETBUF_Type;

/**
 * @brief EMAC configuration structure definition
 */
typedef struct {
	uint32_t	Mode;						/**< Supported EMAC PHY device speed, should be one of the following:
											- EMAC_MODE_AUTO
											- EMAC_MODE_10M_FULL
											- EMAC_MODE_10M_HALF
											- EMAC_MODE_100M_FULL
											- EMAC_MODE_100M_HALF
											*/
	uint8_t 	*pbEMAC_Addr;				/**< Pointer to EMAC Station address that contains 6-bytes
											of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
											*/
} EMAC_CFG_Type;


/**
 * @}
 */


/* Public Functions ----------------------------------------------------------- */
/** @defgroup EMAC_Public_Functions EMAC Public Functions
 * @{
 */
/* Init/DeInit EMAC peripheral */
Status EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
void EMAC_DeInit(void);

/* PHY functions --------------*/
int32_t EMAC_CheckPHYStatus(uint32_t ulPHYState);
int32_t EMAC_SetPHYMode(uint32_t ulPHYMode);
int32_t EMAC_UpdatePHYStatus(void);

/* Filter functions ----------*/
void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState);
void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState);

/* EMAC Packet Buffer functions */
void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
void EMAC_ReadPacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);

/* EMAC Interrupt functions -------*/
void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState);
IntStatus EMAC_IntGetStatus(uint32_t ulIntType);

/* EMAC Index functions -----------*/
Bool EMAC_CheckReceiveIndex(void);
Bool EMAC_CheckTransmitIndex(void);
void EMAC_UpdateRxConsumeIndex(void);
void EMAC_UpdateTxProduceIndex(void);

FlagStatus EMAC_CheckReceiveDataStatus(uint32_t ulRxStatType);
uint32_t EMAC_GetReceiveDataSize(void);
FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode);

/**
 * @}
 */

#ifdef __cplusplus
}
#endif

#endif /* LPC17XX_EMAC_H_ */

/**
 * @}
 */

/* --------------------------------- End Of File ------------------------------ */