lpc17xx_emac.h.svn-base

uCOSII_lwip_lpc1768

 * Macro defines for Status Register
 **********************************************************************/
#define EMAC_SR_RX_EN            0x00000001  	/**< Enable Receive                    */
#define EMAC_SR_TX_EN            0x00000002  	/**< Enable Transmit                   */

/*********************************************************************//**
 * Macro defines for Transmit Status Vector 0 Register
 **********************************************************************/
#define EMAC_TSV0_CRC_ERR        0x00000001  /**< CRC error                         */
#define EMAC_TSV0_LEN_CHKERR     0x00000002  /**< Length Check Error                */
#define EMAC_TSV0_LEN_OUTRNG     0x00000004  /**< Length Out of Range               */
#define EMAC_TSV0_DONE           0x00000008  /**< Tramsmission Completed            */
#define EMAC_TSV0_MCAST          0x00000010  /**< Multicast Destination             */
#define EMAC_TSV0_BCAST          0x00000020  /**< Broadcast Destination             */
#define EMAC_TSV0_PKT_DEFER      0x00000040  /**< Packet Deferred                   */
#define EMAC_TSV0_EXC_DEFER      0x00000080  /**< Excessive Packet Deferral         */
#define EMAC_TSV0_EXC_COLL       0x00000100  /**< Excessive Collision               */
#define EMAC_TSV0_LATE_COLL      0x00000200  /**< Late Collision Occured            */
#define EMAC_TSV0_GIANT          0x00000400  /**< Giant Frame                       */
#define EMAC_TSV0_UNDERRUN       0x00000800  /**< Buffer Underrun                   */
#define EMAC_TSV0_BYTES          0x0FFFF000  /**< Total Bytes Transferred           */
#define EMAC_TSV0_CTRL_FRAME     0x10000000  /**< Control Frame                     */
#define EMAC_TSV0_PAUSE          0x20000000  /**< Pause Frame                       */
#define EMAC_TSV0_BACK_PRESS     0x40000000  /**< Backpressure Method Applied       */
#define EMAC_TSV0_VLAN           0x80000000  /**< VLAN Frame                        */

/*********************************************************************//**
 * Macro defines for Transmit Status Vector 1 Register
 **********************************************************************/
#define EMAC_TSV1_BYTE_CNT       0x0000FFFF  /**< Transmit Byte Count               */
#define EMAC_TSV1_COLL_CNT       0x000F0000  /**< Transmit Collision Count          */

/*********************************************************************//**
 * Macro defines for Receive Status Vector Register
 **********************************************************************/
#define EMAC_RSV_BYTE_CNT        0x0000FFFF  /**< Receive Byte Count                */
#define EMAC_RSV_PKT_IGNORED     0x00010000  /**< Packet Previously Ignored         */
#define EMAC_RSV_RXDV_SEEN       0x00020000  /**< RXDV Event Previously Seen        */
#define EMAC_RSV_CARR_SEEN       0x00040000  /**< Carrier Event Previously Seen     */
#define EMAC_RSV_REC_CODEV       0x00080000  /**< Receive Code Violation            */
#define EMAC_RSV_CRC_ERR         0x00100000  /**< CRC Error                         */
#define EMAC_RSV_LEN_CHKERR      0x00200000  /**< Length Check Error                */
#define EMAC_RSV_LEN_OUTRNG      0x00400000  /**< Length Out of Range               */
#define EMAC_RSV_REC_OK          0x00800000  /**< Frame Received OK                 */
#define EMAC_RSV_MCAST           0x01000000  /**< Multicast Frame                   */
#define EMAC_RSV_BCAST           0x02000000  /**< Broadcast Frame                   */
#define EMAC_RSV_DRIB_NIBB       0x04000000  /**< Dribble Nibble                    */
#define EMAC_RSV_CTRL_FRAME      0x08000000  /**< Control Frame                     */
#define EMAC_RSV_PAUSE           0x10000000  /**< Pause Frame                       */
#define EMAC_RSV_UNSUPP_OPC      0x20000000  /**< Unsupported Opcode                */
#define EMAC_RSV_VLAN            0x40000000  /**< VLAN Frame                        */

/*********************************************************************//**
 * Macro defines for Flow Control Counter Register
 **********************************************************************/
#define EMAC_FCC_MIRR_CNT(n)        	(n&0xFFFF)  		/**< Mirror Counter                    */
#define EMAC_FCC_PAUSE_TIM(n)       	((n&0xFFFF)<<16)  	/**< Pause Timer                       */

/*********************************************************************//**
 * Macro defines for Flow Control Status Register
 **********************************************************************/
#define EMAC_FCS_MIRR_CNT(n)        	(n&0xFFFF)  		/**< Mirror Counter Current            */


/* Receive filter register definitions -------------------------------------------------------- */
/*********************************************************************//**
 * Macro defines for Receive Filter Control Register
 **********************************************************************/
#define EMAC_RFC_UCAST_EN        0x00000001  /**< Accept Unicast Frames Enable      */
#define EMAC_RFC_BCAST_EN        0x00000002  /**< Accept Broadcast Frames Enable    */
#define EMAC_RFC_MCAST_EN        0x00000004  /**< Accept Multicast Frames Enable    */
#define EMAC_RFC_UCAST_HASH_EN   0x00000008  /**< Accept Unicast Hash Filter Frames */
#define EMAC_RFC_MCAST_HASH_EN   0x00000010  /**< Accept Multicast Hash Filter Fram.*/
#define EMAC_RFC_PERFECT_EN      0x00000020  /**< Accept Perfect Match Enable       */
#define EMAC_RFC_MAGP_WOL_EN     0x00001000  /**< Magic Packet Filter WoL Enable    */
#define EMAC_RFC_PFILT_WOL_EN    0x00002000  /**< Perfect Filter WoL Enable         */

/*********************************************************************//**
 * Macro defines for Receive Filter WoL Status/Clear Registers
 **********************************************************************/
#define EMAC_WOL_UCAST           0x00000001  /**< Unicast Frame caused WoL          */
#define EMAC_WOL_BCAST           0x00000002  /**< Broadcast Frame caused WoL        */
#define EMAC_WOL_MCAST           0x00000004  /**< Multicast Frame caused WoL        */
#define EMAC_WOL_UCAST_HASH      0x00000008  /**< Unicast Hash Filter Frame WoL     */
#define EMAC_WOL_MCAST_HASH      0x00000010  /**< Multicast Hash Filter Frame WoL   */
#define EMAC_WOL_PERFECT         0x00000020  /**< Perfect Filter WoL                */
#define EMAC_WOL_RX_FILTER       0x00000080  /**< RX Filter caused WoL              */
#define EMAC_WOL_MAG_PACKET      0x00000100  /**< Magic Packet Filter caused WoL    */
#define EMAC_WOL_BITMASK		 0x01BF		/**< Receive Filter WoL Status/Clear bitmasl value */


/* Module control register definitions ---------------------------------------------------- */
/*********************************************************************//**
 * Macro defines for Interrupt Status/Enable/Clear/Set Registers
 **********************************************************************/
#define EMAC_INT_RX_OVERRUN      0x00000001  /**< Overrun Error in RX Queue         */
#define EMAC_INT_RX_ERR          0x00000002  /**< Receive Error                     */
#define EMAC_INT_RX_FIN          0x00000004  /**< RX Finished Process Descriptors   */
#define EMAC_INT_RX_DONE         0x00000008  /**< Receive Done                      */
#define EMAC_INT_TX_UNDERRUN     0x00000010  /**< Transmit Underrun                 */
#define EMAC_INT_TX_ERR          0x00000020  /**< Transmit Error                    */
#define EMAC_INT_TX_FIN          0x00000040  /**< TX Finished Process Descriptors   */
#define EMAC_INT_TX_DONE         0x00000080  /**< Transmit Done                     */
#define EMAC_INT_SOFT_INT        0x00001000  /**< Software Triggered Interrupt      */
#define EMAC_INT_WAKEUP          0x00002000  /**< Wakeup Event Interrupt            */

/*********************************************************************//**
 * Macro defines for Power Down Register
 **********************************************************************/
#define EMAC_PD_POWER_DOWN       0x80000000  /**< Power Down MAC                    */

/* Descriptor and status formats ---------------------------------------------------- */
/*********************************************************************//**
 * Macro defines for RX Descriptor Control Word
 **********************************************************************/
#define EMAC_RCTRL_SIZE(n)       (n&0x7FF)  	/**< Buffer size field                  */
#define EMAC_RCTRL_INT           0x80000000  	/**< Generate RxDone Interrupt         */

/*********************************************************************//**
 * Macro defines for RX Status Hash CRC Word
 **********************************************************************/
#define EMAC_RHASH_SA            0x000001FF  	/**< Hash CRC for Source Address       */
#define EMAC_RHASH_DA            0x001FF000  	/**< Hash CRC for Destination Address  */

/*********************************************************************//**
 * Macro defines for RX Status Information Word
 **********************************************************************/
#define EMAC_RINFO_SIZE          0x000007FF  /**< Data size in bytes                */
#define EMAC_RINFO_CTRL_FRAME    0x00040000  /**< Control Frame                     */
#define EMAC_RINFO_VLAN          0x00080000  /**< VLAN Frame                        */
#define EMAC_RINFO_FAIL_FILT     0x00100000  /**< RX Filter Failed                  */
#define EMAC_RINFO_MCAST         0x00200000  /**< Multicast Frame                   */
#define EMAC_RINFO_BCAST         0x00400000  /**< Broadcast Frame                   */
#define EMAC_RINFO_CRC_ERR       0x00800000  /**< CRC Error in Frame                */
#define EMAC_RINFO_SYM_ERR       0x01000000  /**< Symbol Error from PHY             */
#define EMAC_RINFO_LEN_ERR       0x02000000  /**< Length Error                      */
#define EMAC_RINFO_RANGE_ERR     0x04000000  /**< Range Error (exceeded max. size)  */
#define EMAC_RINFO_ALIGN_ERR     0x08000000  /**< Alignment Error                   */
#define EMAC_RINFO_OVERRUN       0x10000000  /**< Receive overrun                   */
#define EMAC_RINFO_NO_DESCR      0x20000000  /**< No new Descriptor available       */
#define EMAC_RINFO_LAST_FLAG     0x40000000  /**< Last Fragment in Frame            */
#define EMAC_RINFO_ERR           0x80000000  /**< Error Occured (OR of all errors)  */
#define EMAC_RINFO_ERR_MASK     (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR   | EMAC_RINFO_SYM_ERR | \
EMAC_RINFO_LEN_ERR   | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)

/*********************************************************************//**
 * Macro defines for TX Descriptor Control Word
 **********************************************************************/
#define EMAC_TCTRL_SIZE          0x000007FF  /**< Size of data buffer in bytes      */
#define EMAC_TCTRL_OVERRIDE      0x04000000  /**< Override Default MAC Registers    */
#define EMAC_TCTRL_HUGE          0x08000000  /**< Enable Huge Frame                 */
#define EMAC_TCTRL_PAD           0x10000000  /**< Pad short Frames to 64 bytes      */
#define EMAC_TCTRL_CRC           0x20000000  /**< Append a hardware CRC to Frame    */
#define EMAC_TCTRL_LAST          0x40000000  /**< Last Descriptor for TX Frame      */
#define EMAC_TCTRL_INT           0x80000000  /**< Generate TxDone Interrupt         */

/*********************************************************************//**
 * Macro defines for TX Status Information Word
 **********************************************************************/
#define EMAC_TINFO_COL_CNT       0x01E00000  /**< Collision Count                   */
#define EMAC_TINFO_DEFER         0x02000000  /**< Packet Deferred (not an error)    */
#define EMAC_TINFO_EXCESS_DEF    0x04000000  /**< Excessive Deferral                */
#define EMAC_TINFO_EXCESS_COL    0x08000000  /**< Excessive Collision               */
#define EMAC_TINFO_LATE_COL      0x10000000  /**< Late Collision Occured            */
#define EMAC_TINFO_UNDERRUN      0x20000000  /**< Transmit Underrun                 */
#define EMAC_TINFO_NO_DESCR      0x40000000  /**< No new Descriptor available       */
#define EMAC_TINFO_ERR           0x80000000  /**< Error Occured (OR of all errors)  */

#ifdef MCB_LPC_1768
/* DP83848C PHY definition ------------------------------------------------------------ */

/** PHY device reset time out definition */
#define EMAC_PHY_RESP_TOUT		0x100000UL

/* ENET Device Revision ID */
#define EMAC_OLD_EMAC_MODULE_ID  0x39022000  /**< Rev. ID for first rev '-'         */

/*********************************************************************//**
 * Macro defines for DP83848C PHY Registers
 **********************************************************************/
#define EMAC_PHY_REG_BMCR        0x00        /**< Basic Mode Control Register       */
#define EMAC_PHY_REG_BMSR        0x01        /**< Basic Mode Status Register        */
#define EMAC_PHY_REG_IDR1        0x02        /**< PHY Identifier 1                  */
#define EMAC_PHY_REG_IDR2        0x03        /**< PHY Identifier 2                  */
#define EMAC_PHY_REG_ANAR        0x04        /**< Auto-Negotiation Advertisement    */
#define EMAC_PHY_REG_ANLPAR      0x05        /**< Auto-Neg. Link Partner Abitily    */
#define EMAC_PHY_REG_ANER        0x06        /**< Auto-Neg. Expansion Register      */
#define EMAC_PHY_REG_ANNPTR      0x07        /**< Auto-Neg. Next Page TX            */
#define EMAC_PHY_REG_LPNPA		 0x08

/*********************************************************************//**
 * Macro defines for PHY Extended Registers
 **********************************************************************/
#define EMAC_PHY_REG_STS         0x10        /**< Status Register                   */
#define EMAC_PHY_REG_MICR        0x11        /**< MII Interrupt Control Register    */
#define EMAC_PHY_REG_MISR        0x12        /**< MII Interrupt Status Register     */
#define EMAC_PHY_REG_FCSCR       0x14        /**< False Carrier Sense Counter       */
#define EMAC_PHY_REG_RECR        0x15        /**< Receive Error Counter             */
#define EMAC_PHY_REG_PCSR        0x16        /**< PCS Sublayer Config. and Status   */
#define EMAC_PHY_REG_RBR         0x17        /**< RMII and Bypass Register          */
#define EMAC_PHY_REG_LEDCR       0x18        /**< LED Direct Control Register       */
#define EMAC_PHY_REG_PHYCR       0x19        /**< PHY Control Register              */
#define EMAC_PHY_REG_10BTSCR     0x1A        /**< 10Base-T Status/Control Register  */
#define EMAC_PHY_REG_CDCTRL1     0x1B        /**< CD Test Control and BIST Extens.  */
#define EMAC_PHY_REG_EDCR        0x1D        /**< Energy Detect Control Register    */

/*********************************************************************//**
 * Macro defines for PHY Basic Mode Control Register
 **********************************************************************/
#define EMAC_PHY_BMCR_RESET     			(1<<15)		/**< Reset bit */
#define EMAC_PHY_BMCR_LOOPBACK      		(1<<14)		/**< Loop back */
#define EMAC_PHY_BMCR_SPEED_SEL     		(1<<13)		/**< Speed selection */
#define EMAC_PHY_BMCR_AN					(1<<12)		/**< Auto Negotiation */
#define EMAC_PHY_BMCR_POWERDOWN				(1<<11)		/**< Power down mode */
#define EMAC_PHY_BMCR_ISOLATE				(1<<10)		/**< Isolate */
#define EMAC_PHY_BMCR_RE_AN					(1<<9)		/**< Restart auto negotiation */
#define EMAC_PHY_BMCR_DUPLEX				(1<<8)		/**< Duplex mode */

/*********************************************************************//**
 * Macro defines for PHY Basic Mode Status Status Register
 **********************************************************************/
#define EMAC_PHY_BMSR_100BE_T4        	   	(1<<15)		/**< 100 base T4 */
#define EMAC_PHY_BMSR_100TX_FULL			(1<<14)		/**< 100 base full duplex */
#define EMAC_PHY_BMSR_100TX_HALF			(1<<13)		/**< 100 base half duplex */
#define EMAC_PHY_BMSR_10BE_FULL				(1<<12)		/**< 10 base T full duplex */
#define EMAC_PHY_BMSR_10BE_HALF				(1<<11)		/**< 10 base T half duplex */
#define EMAC_PHY_BMSR_NOPREAM				(1<<6)		/**< MF Preamable Supress */
#define EMAC_PHY_BMSR_AUTO_DONE				(1<<5)		/**< Auto negotiation complete */
#define EMAC_PHY_BMSR_REMOTE_FAULT			(1<<4)		/**< Remote fault */
#define EMAC_PHY_BMSR_NO_AUTO				(1<<3)		/**< Auto Negotiation ability */
#define EMAC_PHY_BMSR_LINK_ESTABLISHED		(1<<2)		/**< Link status */

/*********************************************************************//**
 * Macro defines for PHY Status Register
 **********************************************************************/
#define EMAC_PHY_SR_REMOTE_FAULT   			(1<<6)		/**< Remote Fault */