lpc17xx_clkpwr.h.svn-base

uCOSII_lwip_lpc1768

/**********************************************************************
* $Id$		lpc17xx_clkpwr.h			2010-05-21
*//**
* @file		lpc17xx_clkpwr.h
* @brief	Contains all macro definitions and function prototypes
* 			support for Clock and Power Control firmware library on LPC17xx
* @version	2.0
* @date		21. May. 2010
* @author	NXP MCU SW Application Team
*
* Copyright(C) 2010, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/

/* Peripheral group ----------------------------------------------------------- */
/** @defgroup CLKPWR CLKPWR
 * @ingroup LPC1700CMSIS_FwLib_Drivers
 * @{
 */

#ifndef LPC17XX_CLKPWR_H_
#define LPC17XX_CLKPWR_H_

/* Includes ------------------------------------------------------------------- */
#include "lpc17xx.h"
#include "lpc_types.h"

#ifdef __cplusplus
extern "C"
{
#endif

/* Public Macros -------------------------------------------------------------- */
/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
 * @{
 */

/**********************************************************************
 * Peripheral Clock Selection Definitions
 **********************************************************************/
/** Peripheral clock divider bit position for WDT */
#define	CLKPWR_PCLKSEL_WDT  		((uint32_t)(0))
/** Peripheral clock divider bit position for TIMER0 */
#define	CLKPWR_PCLKSEL_TIMER0  		((uint32_t)(2))
/** Peripheral clock divider bit position for TIMER1 */
#define	CLKPWR_PCLKSEL_TIMER1  		((uint32_t)(4))
/** Peripheral clock divider bit position for UART0 */
#define	CLKPWR_PCLKSEL_UART0  		((uint32_t)(6))
/** Peripheral clock divider bit position for UART1 */
#define	CLKPWR_PCLKSEL_UART1  		((uint32_t)(8))
/** Peripheral clock divider bit position for PWM1 */
#define	CLKPWR_PCLKSEL_PWM1  		((uint32_t)(12))
/** Peripheral clock divider bit position for I2C0 */
#define	CLKPWR_PCLKSEL_I2C0  		((uint32_t)(14))
/** Peripheral clock divider bit position for SPI */
#define	CLKPWR_PCLKSEL_SPI  		((uint32_t)(16))
/** Peripheral clock divider bit position for SSP1 */
#define	CLKPWR_PCLKSEL_SSP1  		((uint32_t)(20))
/** Peripheral clock divider bit position for DAC */
#define	CLKPWR_PCLKSEL_DAC  		((uint32_t)(22))
/** Peripheral clock divider bit position for ADC */
#define	CLKPWR_PCLKSEL_ADC  		((uint32_t)(24))
/** Peripheral clock divider bit position for CAN1 */
#define	CLKPWR_PCLKSEL_CAN1 		((uint32_t)(26))
/** Peripheral clock divider bit position for CAN2 */
#define	CLKPWR_PCLKSEL_CAN2 		((uint32_t)(28))
/** Peripheral clock divider bit position for ACF */
#define	CLKPWR_PCLKSEL_ACF  		((uint32_t)(30))
/** Peripheral clock divider bit position for QEI */
#define	CLKPWR_PCLKSEL_QEI  		((uint32_t)(32))
/** Peripheral clock divider bit position for PCB */
#define	CLKPWR_PCLKSEL_PCB  		((uint32_t)(36))
/** Peripheral clock divider bit position for  I2C1 */
#define	CLKPWR_PCLKSEL_I2C1  		((uint32_t)(38))
/** Peripheral clock divider bit position for SSP0 */
#define	CLKPWR_PCLKSEL_SSP0  		((uint32_t)(42))
/** Peripheral clock divider bit position for TIMER2 */
#define	CLKPWR_PCLKSEL_TIMER2  		((uint32_t)(44))
/** Peripheral clock divider bit position for  TIMER3 */
#define	CLKPWR_PCLKSEL_TIMER3  		((uint32_t)(46))
/** Peripheral clock divider bit position for UART2 */
#define	CLKPWR_PCLKSEL_UART2  		((uint32_t)(48))
/** Peripheral clock divider bit position for UART3 */
#define	CLKPWR_PCLKSEL_UART3  		((uint32_t)(50))
/** Peripheral clock divider bit position for I2C2 */
#define	CLKPWR_PCLKSEL_I2C2  		((uint32_t)(52))
/** Peripheral clock divider bit position for I2S */
#define	CLKPWR_PCLKSEL_I2S  		((uint32_t)(54))
/** Peripheral clock divider bit position for RIT */
#define	CLKPWR_PCLKSEL_RIT  		((uint32_t)(58))
/** Peripheral clock divider bit position for SYSCON */
#define	CLKPWR_PCLKSEL_SYSCON  		((uint32_t)(60))
/** Peripheral clock divider bit position for MC */
#define	CLKPWR_PCLKSEL_MC  			((uint32_t)(62))

/** Macro for Peripheral Clock Selection register bit values
 * Note: When CCLK_DIV_8, Peripheral抯 clock is selected to
 * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
 * when