mcbspaic.asm

TI公司DSP开发板DSK5402针对DTMF的完整功能操作与代码

***********************************************************
* McBSP_Reset & AIC_Reset                                 *
* Objective:                                              *
* Reset and Initialize McBSP and AIC                      *
***********************************************************
	.def 	McBSP_AIC_Init  
	.mmregs 
;DSP McBSP Register Definitions			
DRR11	.set	0x41	;McBSP data receive register 1
DXR11	.set	0x43	;McBSP data transmit register 1
SPSA1	.set	0x48	;McBSP sub -address register
SPSD1	.set	0x49 	;McBSP sub -bank data register
SPCR11	.set	0x00	;McBSP serial port control register 1
SPCR21	.set	0x01 	;McBSP serial port control register 2
RCR11	.set	0x02    ;McBSP receive control register 1
RCR21	.set	0x03    ;McBSP receive control register 2
XCR11	.set	0x04	;McBSP transmit control register 1
XCR21	.set	0x05	;McBSP transmit control register 2
SRGR11	.set	0x06	;McBSP sample rate generator register 1
SRGR21	.set	0x07	;McBSP sample rate generator register 2
MCR11	.set	0x08	;McBSP multichannel register 1
MCR21	.set	0x09	;McBSP multichannel register 2
RCERA1	.set	0x0A	;McBSP receive channel enable register partition A
RCERA2	.set	0x0B	;McBSP receive channel enable register partition B
XCERA1	.set	0x0C	;McBSP transmit channel enable register partition A
XCERA2	.set	0x0D	;McBSP transmit channel enable register partition B
PCR1	.set	0x0E	;McBSp pin control register
DMPREC	.set	0x54    ;DMA Channel Priority and Enable Control Register
CTRL2	.set	0x04

	.data
dummy	.word	0	

	.text   
McBSP_AIC_Init:  
	CALL McBSP_Init		
	CALL Codec_Reset
	IMR=#0400h	; Enable BRINT1 & BXINT1
	mmr(DXR11)=#0h	; Clear transmit register		
	RETURN
	
McBSP_Init:
	mmr(SPSA1)=#SPCR11	;SPCR1
	mmr(SPSD1)=#0h		;setting RRST to 0	
	mmr(SPSA1)=#SPCR21	;SPCR2
	mmr(SPSD1)=#0h		;setting XRST to 0
	mmr(SPSA1)=#RCR11	;RCR
	mmr(SPSD1)=#40h		;Use 16 bit word -length, defaults to 				
				;frame length of 1 sample per FS
 	mmr(SPSA1)=#RCR21	;single phase no companding
	mmr(SPSD1)=#0h		;MSB first, don't ignore FS, delay 0
	mmr(SPSA1)=#XCR11	;XCR
	mmr(SPSD1)=#40h		;the same as RCR
	mmr(SPSA1)=#XCR21
	mmr(SPSD1)=#0h
	mmr(SPSA1)=#SRGR11	;SRGR
        mmr(SPSD1)=#0h		;FWID CLKGDV           
	mmr(SPSA1)=#SRGR21	;Free run, rising edge, use CLKS pin
	mmr(SPSD1)=#0h 	
	mmr(SPSA1)=#MCR11	;Multichannel Control Register 1
        mmr(SPSD1)=#0h           
	mmr(SPSA1)=#MCR21	;Multichannel Control Register 2
	mmr(SPSD1)=#0h
	mmr(SPSA1)=#RCERA1	;RCERA
	mmr(SPSD1)=#0h	                           
	mmr(SPSA1)=#RCERA2
	mmr(SPSD1)=#0h
	mmr(SPSA1)=#XCERA1	;XCERA
        mmr(SPSD1)=#0h           
	mmr(SPSA1)=#XCERA2
	mmr(SPSD1)=#0h
	mmr(SPSA1)=#PCR1	;PCR
        mmr(SPSD1)=#1101b                       
        mmr(DMPREC)=#0FF3Fh	;DMPREC  DMA                    
        mmr(DXR11)=#0h		;Clear DXR                         
	mmr(SPSA1)=#SPCR11	;SPCR
	mmr(SPSD1)=#01h		;Enable serial port (RX)	
	mmr(SPSA1)=#SPCR21	;Enable serial port (TX)
	mmr(SPSD1)=#01h	
	RETURN
		
Codec_Reset:
	IMR=#0400h
	AR1=#dummy

***********************************************************
* Control Register 1
* D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
*  1  -  -  -  -  -  -  - Software reset
*  0  -  -  -  -  -  -  - Software reset not asserted
*  -  1  -  -  -  -  -  - Software power down (analog and filters)
*  -  0  -  -  -  -  -  - Software power down (not asserted)
*  -  -  1  -  -  -  -  - Select AUXP and AUXM for ADC
*  -  -  0  -  -  -  -  - Select INP and INM for ADC
*  -  -  -  0  -  -  -  - Select INP and INM for monitor
*  -  -  -  1  -  -  -  - Select AUXP and AUXM for monitor
*  -  -  -  -  1  1  -  - Monitor amplifier gain =  - 18 dB (see Note 1)
*  -  -  -  -  1  0  -  - Monitor amplifier gain =  - 8 dB (see Note 1)
*  -  -  -  -  0  1  -  - Monitor amplifier gain = 0 dB (see Note 1)
*  -  -  -  -  0  0  -  - Monitor amp mute
*  -  -  -  -  -  -  1  - Digital loopback asserted
*  -  -  -  -  -  -  0  - Digital loopback not asserted
*  -  -  -  -  -  -  -  1 16 -bit DAC mode (hardware secondary requests)
*  -  -  -  -  -  -  -  0 Not 16 -bit DAC mode (software secondary requests) [(15+1) - bit mode]
***********************************************************
;step 0     
	A=#80h		;Send software reset
	B=#1h
        CALL Codec_reg_write

;step 1
	A=#01h		;16 -bit DAC mode
	B=#1h		;write to AIC Control register 1
        CALL Codec_reg_write

***********************************************************
* Control Register 2
* D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
*  X  -  -  -  -  -  -  - FLAG output value
*  -  1  -  -  -  -  -  - Phone mode enable
*  -  0  -  -  -  -  -  - Phone mode disable
*  -  -  X  -  -  -  -  - Decimator FIR overflow flag (valid only during read cycle)
*  -  -  -  1  -  -  -  - 16-bit ADC mode
*  -  -  -  0  -  -  -  - Not-16-bit ADC mode [(15+1) - bit mode]
*  -  -  -  -  -  X  0  0 Reserved (TLC320AD50C only)
*  -  -  -  -  -  0  0  0 FSD enable (TLC320AD52C only)
*  -  -  -  -  -  1  -  - FSD disable (TLC320AD52C only)
*  -  -  -  -  1  -  -  - Analog loopback enabled
*  -  -  -  -  0  -  -  - Analog loopback disabled
***********************************************************
;step 2
	A=#10h		;16-bit ADC mode
	B=#2h		;write to AIC Control register 2
        CALL Codec_reg_write

***********************************************************
* Control Register 3
* D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
*  -  -  X  X  X  X  X  X Number of SCLKs between FS and FSD
*  X  X  -  -  -  -  -  - Binary number of slave devices (3 maximum for TLC320AC50C,
* 						   1 maximum for TLC320AC52C)
***********************************************************
;step 3
	A=#3Fh		;0 slaves, 63 SCLKs between FS and FSD
	B=#3h		;write to AIC Control register 3
        CALL Codec_reg_write                                

***********************************************************
* Control Register 4
* D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
*  -  -  -  -  1  1  -  - Analog input gain = mute
*  -  -  -  -  1  0  -  - Analog input gain = 12 dB
*  -  -  -  -  0  1  -  - Analog input gain = 6 dB
*  -  -  -  -  0  0  -  - Analog input gain = 0 dB
*  -  -  -  -  -  -  1  1 Analog output gain = mute
*  -  -  -  -  -  -  1  0 Analog output gain =  - 12 dB
*  -  -  -  -  -  -  0  1 Analog output gain =  - 6 dB
*  -  -  -  -  -  -  0  0 Analog output gain = 0 dB
*  -  X  X  X  -  -  -  - Sample frequency select (N): f s = MCLK/(128 x N) or MCLK/(512 x N)
*  1  -  -  -  -  -  -  - Bypass internal DPLL
*  0  -  -  -  -  -  -  - Enable internal DPLL                   
*
* D4-D6: 001=1, 010=2, etc. By setting D4-D6 to 000, N = 8 is selected.
***********************************************************
;step 4
	A=#0A2h		;8KHz sampling rate, bypass PLL,analog input and output gain = 0
	B=#4h		;write to AIC Control register 4
        CALL Codec_reg_write
            
	RETURN

Codec_reg_write:  	;Write an AD50 control register
	A=A | B<<8	;Insert codec register address
	IFR=#0400h
	B=mmr(DRR11)	;Perform dummy READ to clear RRDY			
	IFR=#0400h
	IDLE(1)         ;Wait for RRDY asserted

	B=mmr(DRR11)	;Perform dummy read of primary slot		              
	*AR1=PORT(CTRL2)   ;Set FC to request secondary communications
	NOP
	*AR1=*AR1 | #08h
	NOP
	PORT(CTRL2)=*AR1
			
	IFR=#0400h
	IDLE(1)
			
	B=mmr(DRR11)	;Perform dummy read of primary slot and clear FC
	mmr(DXR11)=A	;Write data for next secondary communications slot
			
	*AR1=PORT(CTRL2)   ;Clear FC to disable further secondary communications
	NOP
	*AR1=*AR1 & #0FFF7h
	NOP
	PORT(CTRL2)=*AR1
			
	IFR=#0400h
	IDLE(1)		;Wait for RRDY asserted
			
	B=mmr(DRR11)	;Perform dummy read on secondary slot
	mmr(DXR11)=#0h	;Write 0 for next primary slot
	RETURN