ops2.c

uboot在arm处理器s3c2410的移植代码

	    destval = fetch_data_long(destoffset);
	    destval = shrd_long(destval,*shiftreg,M.x86.R_CL);
	    store_data_long(destoffset, destval);
	} else {
	    u16 destval;
	    u16 *shiftreg;

	    destoffset = decode_rm00_address(rl);
	    DECODE_PRINTF(",");
	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
	    DECODE_PRINTF(",CL\n");
	    TRACE_AND_STEP();
	    destval = fetch_data_word(destoffset);
	    destval = shrd_word(destval,*shiftreg,M.x86.R_CL);
	    store_data_word(destoffset, destval);
	}
	break;
    case 1:
	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
	    u32 destval;
	    u32 *shiftreg;

	    destoffset = decode_rm01_address(rl);
	    DECODE_PRINTF(",");
	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
	    DECODE_PRINTF(",CL\n");
	    TRACE_AND_STEP();
	    destval = fetch_data_long(destoffset);
	    destval = shrd_long(destval,*shiftreg,M.x86.R_CL);
	    store_data_long(destoffset, destval);
	} else {
	    u16 destval;
	    u16 *shiftreg;

	    destoffset = decode_rm01_address(rl);
	    DECODE_PRINTF(",");
	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
	    DECODE_PRINTF(",CL\n");
	    TRACE_AND_STEP();
	    destval = fetch_data_word(destoffset);
	    destval = shrd_word(destval,*shiftreg,M.x86.R_CL);
	    store_data_word(destoffset, destval);
	}
	break;
    case 2:
	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
	    u32 destval;
	    u32 *shiftreg;

	    destoffset = decode_rm10_address(rl);
	    DECODE_PRINTF(",");
	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
	    DECODE_PRINTF(",CL\n");
	    TRACE_AND_STEP();
	    destval = fetch_data_long(destoffset);
	    destval = shrd_long(destval,*shiftreg,M.x86.R_CL);
	    store_data_long(destoffset, destval);
	} else {
	    u16 destval;
	    u16 *shiftreg;

	    destoffset = decode_rm10_address(rl);
	    DECODE_PRINTF(",");
	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
	    DECODE_PRINTF(",CL\n");
	    TRACE_AND_STEP();
	    destval = fetch_data_word(destoffset);
	    destval = shrd_word(destval,*shiftreg,M.x86.R_CL);
	    store_data_word(destoffset, destval);
	}
	break;
    case 3:                     /* register to register */
	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
	    u32 *destreg,*shiftreg;

	    destreg = DECODE_RM_LONG_REGISTER(rl);
	    DECODE_PRINTF(",");
	    shiftreg = DECODE_RM_LONG_REGISTER(rh);
	    DECODE_PRINTF(",CL\n");
	    TRACE_AND_STEP();
	    *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL);
	} else {
	    u16 *destreg,*shiftreg;

	    destreg = DECODE_RM_WORD_REGISTER(rl);
	    DECODE_PRINTF(",");
	    shiftreg = DECODE_RM_WORD_REGISTER(rh);
	    DECODE_PRINTF(",CL\n");
	    TRACE_AND_STEP();
	    *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL);
	}
	break;
    }
    DECODE_CLEAR_SEGOVR();
    END_OF_INSTR();
}

/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xaf
****************************************************************************/
void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2))
{
    int mod, rl, rh;
    uint srcoffset;

    START_OF_INSTR();
    DECODE_PRINTF("IMUL\t");
    FETCH_DECODE_MODRM(mod, rh, rl);
    switch (mod) {
    case 0:
	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
	    u32 *destreg;
	    u32 srcval;
	    u32 res_lo,res_hi;

	    destreg = DECODE_RM_LONG_REGISTER(rh);
	    DECODE_PRINTF(",");
	    srcoffset = decode_rm00_address(rl);
	    srcval = fetch_data_long(srcoffset);
	    TRACE_AND_STEP();
	    imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval);
	    if (res_hi != 0) {
		SET_FLAG(F_CF);
		SET_FLAG(F_OF);
	    } else {
		CLEAR_FLAG(F_CF);
		CLEAR_FLAG(F_OF);
	    }
	    *destreg = (u32)res_lo;
	} else {
	    u16 *destreg;
	    u16 srcval;
	    u32 res;

	    destreg = DECODE_RM_WORD_REGISTER(rh);
	    DECODE_PRINTF(",");
	    srcoffset = decode_rm00_address(rl);
	    srcval = fetch_data_word(srcoffset);
	    TRACE_AND_STEP();
	    res = (s16)*destreg * (s16)srcval;
	    if (res > 0xFFFF) {
		SET_FLAG(F_CF);
		SET_FLAG(F_OF);
	    } else {
		CLEAR_FLAG(F_CF);
		CLEAR_FLAG(F_OF);
	    }
	    *destreg = (u16)res;
	}
	break;
    case 1:
	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
	    u32 *destreg;
	    u32 srcval;
	    u32 res_lo,res_hi;

	    destreg = DECODE_RM_LONG_REGISTER(rh);
	    DECODE_PRINTF(",");
	    srcoffset = decode_rm01_address(rl);
	    srcval = fetch_data_long(srcoffset);
	    TRACE_AND_STEP();
	    imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval);
	    if (res_hi != 0) {
		SET_FLAG(F_CF);
		SET_FLAG(F_OF);
	    } else {
		CLEAR_FLAG(F_CF);
		CLEAR_FLAG(F_OF);
	    }
	    *destreg = (u32)res_lo;
	} else {
	    u16 *destreg;
	    u16 srcval;
	    u32 res;

	    destreg = DECODE_RM_WORD_REGISTER(rh);
	    DECODE_PRINTF(",");
	    srcoffset = decode_rm01_address(rl);
	    srcval = fetch_data_word(srcoffset);
	    TRACE_AND_STEP();
	    res = (s16)*destreg * (s16)srcval;
	    if (res > 0xFFFF) {
		SET_FLAG(F_CF);
		SET_FLAG(F_OF);
	    } else {
		CLEAR_FLAG(F_CF);
		CLEAR_FLAG(F_OF);
	    }
	    *destreg = (u16)res;
	}
	break;
    case 2:
	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
	    u32 *destreg;
	    u32 srcval;
	    u32 res_lo,res_hi;

	    destreg = DECODE_RM_LONG_REGISTER(rh);
	    DECODE_PRINTF(",");
	    srcoffset = decode_rm10_address(rl);
	    srcval = fetch_data_long(srcoffset);
	    TRACE_AND_STEP();
	    imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval);
	    if (res_hi != 0) {
		SET_FLAG(F_CF);
		SET_FLAG(F_OF);
	    } else {
		CLEAR_FLAG(F_CF);
		CLEAR_FLAG(F_OF);
	    }
	    *destreg = (u32)res_lo;
	} else {
	    u16 *destreg;
	    u16 srcval;
	    u32 res;

	    destreg = DECODE_RM_WORD_REGISTER(rh);
	    DECODE_PRINTF(",");
	    srcoffset = decode_rm10_address(rl);
	    srcval = fetch_data_word(srcoffset);
	    TRACE_AND_STEP();
	    res = (s16)*destreg * (s16)srcval;
	    if (res > 0xFFFF) {
		SET_FLAG(F_CF);
		SET_FLAG(F_OF);
	    } else {
		CLEAR_FLAG(F_CF);
		CLEAR_FLAG(F_OF);
	    }
	    *destreg = (u16)res;
	}
	break;
    case 3:                     /* register to register */
	if (M.x86.mode & SYSMODE_PREFIX_DATA) {
	    u32 *destreg,*srcreg;
	    u32 res_lo,res_hi;

	    destreg = DECODE_RM_LONG_REGISTER(rh);
	    DECODE_PRINTF(",");
	    srcreg = DECODE_RM_LONG_REGISTER(rl);
	    TRACE_AND_STEP();
	    imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg);
	    if (res_hi != 0) {
		SET_FLAG(F_CF);
		SET_FLAG(F_OF);
	    } else {
		CLEAR_FLAG(F_CF);
		CLEAR_FLAG(F_OF);
	    }
	    *destreg = (u32)res_lo;
	} else {
	    u16 *destreg,*srcreg;
	    u32 res;

	    destreg = DECODE_RM_WORD_REGISTER(rh);
	    DECODE_PRINTF(",");
	    srcreg = DECODE_RM_WORD_REGISTER(rl);
	    res = (s16)*destreg * (s16)*srcreg;
	    if (res > 0xFFFF) {
		SET_FLAG(F_CF);
		SET_FLAG(F_OF);
	    } else {
		CLEAR_FLAG(F_CF);
		CLEAR_FLAG(F_OF);
	    }
	    *destreg = (u16)res;
	}
	break;
    }
    DECODE_CLEAR_SEGOVR();
    END_OF_INSTR();
}

/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xb2
****************************************************************************/
void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2))
{
	int mod, rh, rl;
    u16 *dstreg;
    uint srcoffset;

    START_OF_INSTR();
    DECODE_PRINTF("LSS\t");
    FETCH_DECODE_MODRM(mod, rh, rl);
    switch (mod) {
    case 0:
	dstreg = DECODE_RM_WORD_REGISTER(rh);
	DECODE_PRINTF(",");
	srcoffset = decode_rm00_address(rl);
	DECODE_PRINTF("\n");
	TRACE_AND_STEP();
	*dstreg = fetch_data_word(srcoffset);
	M.x86.R_SS = fetch_data_word(srcoffset + 2);
	break;
    case 1:
	dstreg = DECODE_RM_WORD_REGISTER(rh);
	DECODE_PRINTF(",");
	srcoffset = decode_rm01_address(rl);
	DECODE_PRINTF("\n");
	TRACE_AND_STEP();
	*dstreg = fetch_data_word(srcoffset);
	M.x86.R_SS = fetch_data_word(srcoffset + 2);
	break;
    case 2:
	dstreg = DECODE_RM_WORD_REGISTER(rh);
	DECODE_PRINTF(",");
	srcoffset = decode_rm10_address(rl);
	DECODE_PRINTF("\n");
	TRACE_AND_STEP();
	*dstreg = fetch_data_word(srcoffset);
	M.x86.R_SS = fetch_data_word(srcoffset + 2);
	break;
    case 3:                     /* register to register */
	/* UNDEFINED! */
	TRACE_AND_STEP();
    }
    DECODE_CLEAR_SEGOVR();
    END_OF_INSTR();
}

/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xb3
****************************************************************************/
void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2))
{
	int mod, rl, rh;
	uint srcoffset;
	int bit,disp;

	START_OF_INSTR();
	DECODE_PRINTF("BTR\t");
	FETCH_DECODE_MODRM(mod, rh, rl);
	switch (mod) {
	case 0:
		if (M.x86.mode & SYSMODE_PREFIX_DATA) {
			u32 srcval,mask;
			u32 *shiftreg;

			srcoffset = decode_rm00_address(rl);
			DECODE_PRINTF(",");
			shiftreg = DECODE_RM_LONG_REGISTER(rh);
			TRACE_AND_STEP();
			bit = *shiftreg & 0x1F;
			disp = (s16)*shiftreg >> 5;
			srcval = fetch_data_long(srcoffset+disp);
			mask = (0x1 << bit);
			CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
			store_data_long(srcoffset+disp, srcval & ~mask);
		} else {
			u16 srcval,mask;
			u16 *shiftreg;

			srcoffset = decode_rm00_address(rl);
			DECODE_PRINTF(",");
			shiftreg = DECODE_RM_WORD_REGISTER(rh);
			TRACE_AND_STEP();
			bit = *shiftreg & 0xF;
			disp = (s16)*shiftreg >> 4;
			srcval = fetch_data_word(srcoffset+disp);
			mask = (u16)(0x1 << bit);
			CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
			store_data_word(srcoffset+disp, (u16)(srcval & ~mask));
		}
		break;
	case 1:
		if (M.x86.mode & SYSMODE_PREFIX_DATA) {
			u32 srcval,mask;
			u32 *shiftreg;

			srcoffset = decode_rm01_address(rl);
			DECODE_PRINTF(",");
			shiftreg = DECODE_RM_LONG_REGISTER(rh);
			TRACE_AND_STEP();
			bit = *shiftreg & 0x1F;
			disp = (s16)*shiftreg >> 5;
			srcval = fetch_data_long(srcoffset+disp);
			mask = (0x1 << bit);
			CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
			store_data_long(srcoffset+disp, srcval & ~mask);
		} else {
			u16 srcval,mask;
			u16 *shiftreg;

			srcoffset = decode_rm01_address(rl);
			DECODE_PRINTF(",");
			shiftreg = DECODE_RM_WORD_REGISTER(rh);
			TRACE_AND_STEP();
			bit = *shiftreg & 0xF;
			disp = (s16)*shiftreg >> 4;
			srcval = fetch_data_word(srcoffset+disp);
			mask = (u16)(0x1 << bit);
			CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
			store_data_word(srcoffset+disp, (u16)(srcval & ~mask));
		}
		break;
	case 2:
		if (M.x86.mode & SYSMODE_PREFIX_DATA) {
			u32 srcval,mask;
			u32 *shiftreg;

			srcoffset = decode_rm10_address(rl);
			DECODE_PRINTF(",");
			shiftreg = DECODE_RM_LONG_REGISTER(rh);
			TRACE_AND_STEP();
			bit = *shiftreg & 0x1F;
			disp = (s16)*shiftreg >> 5;
			srcval = fetch_data_long(srcoffset+disp);
			mask = (0x1 << bit);
			CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
			store_data_long(srcoffset+disp, srcval & ~mask);
		} else {
			u16 srcval,mask;
			u16 *shiftreg;

			srcoffset = decode_rm10_address(rl);
			DECODE_PRINTF(",");
			shiftreg = DECODE_RM_WORD_REGISTER(rh);
			TRACE_AND_STEP();
			bit = *shiftreg & 0xF;
			disp = (s16)*shiftreg >> 4;
			srcval = fetch_data_word(srcoffset+disp);
			mask = (u16)(0x1 << bit);
			CONDITIONAL_SET_FLAG(srcval & mask,F_CF);
			store_data_word(srcoffset+disp, (u16)(srcval & ~mask));
		}
		break;
	case 3:                     /* register to register */
		if (M.x86.mode & SYSMODE_PREFIX_DATA) {
			u32 *srcreg,*shiftreg;
			u32 mask;

			srcreg = DECODE_RM_LONG_REGISTER(rl);
			DECODE_PRINTF(",");
			shiftreg = DECODE_RM_LONG_REGISTER(rh);
			TRACE_AND_STEP();
			bit = *shiftreg & 0x1F;
			mask = (0x1 << bit);
			CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
			*srcreg &= ~mask;
		} else {
			u16 *srcreg,*shiftreg;
			u16 mask;

			srcreg = DECODE_RM_WORD_REGISTER(rl);
			DECODE_PRINTF(",");
			shiftreg = DECODE_RM_WORD_REGISTER(rh);
			TRACE_AND_STEP();
			bit = *shiftreg & 0xF;
			mask = (u16)(0x1 << bit);
			CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF);
			*srcreg &= ~mask;
		}
		break;
	}
	DECODE_CLEAR_SEGOVR();
	END_OF_INSTR();
}

/****************************************************************************
REMARKS:
Handles opcode 0x0f,0xb4
****************************************************************************/
void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2))
{
	int mod, rh, rl;
    u16 *dstreg;
    uint srcoffset;

    START_OF_INSTR();
    DECODE_PRINTF("LFS\t");
    FETCH_DECODE_MODRM(mod, rh, rl);
    switch (mod) {
    case 0:
	dstreg = DECODE_RM_WORD_REGISTER(rh);
	DECODE_PRINTF(",");
	srcoffset = decode_rm00_address(rl);
	DECODE_PRINTF("\n");
	TRACE_AND_STEP();
	*dstreg = fetch_data_word(srcoffset);
	M.x86.R_FS = fetch_data_word(srcoffset + 2);
	break;
    case 1:
	dstreg = DECODE_RM_WORD_REGISTER(rh);
	DECODE_PRINTF(",");
	srcoffset = decode_rm01_address(rl);
	DECODE_PRINTF("\n");
	TRACE_AND_STEP();
	*dstreg = fetch_data_word(srcoffset);
	M.x86.R_FS = fetch_data_word(srcoffset + 2);
	break;
    case 2:
	dstreg = DECODE_RM_WORD_REGISTER(rh);
	DECODE_PRINTF(",");
	srcoffset = decode_rm10_address(rl);
	DECODE_PRINTF("\n");