pip405.c

uboot在arm处理器s3c2410的移植代码

	baseaddr += bank_size;
	sdram_size += bank_size;

	/* write SDRAM bank 2 register */
	mtdcr (memcfga, mem_mb2cf);
	mtdcr (memcfgd, bank);

	/* get SDRAM bank 3 register */
	mtdcr (memcfga, mem_mb3cf);
	bank = mfdcr (memcfgd) & ~0xFFCEE001;

#ifdef SDRAM_DEBUG
	serial_puts ("bank3: baseaddr: ");
	write_4hex (baseaddr);
	serial_puts (" banksize: ");
	write_4hex (bank_size);
#endif

	if (banks == 2) {
		bank |= (baseaddr | tmp | 0x01);
		baseaddr += bank_size;
		sdram_size += bank_size;
	}
	/* endif */
#ifdef SDRAM_DEBUG
	serial_puts (" mb3cf: ");
	write_4hex (bank);
	serial_puts ("\n");
#endif

	/* write SDRAM bank 3 register */
	mtdcr (memcfga, mem_mb3cf);
	mtdcr (memcfgd, bank);


	/* get SDRAM refresh interval register */
	mtdcr (memcfga, mem_rtr);
	tmp = mfdcr (memcfgd) & ~0x3FF80000;

	if (tmemclk < NSto10PS (16))
		tmp |= 0x05F00000;
	else
		tmp |= 0x03F80000;

	/* write SDRAM refresh interval register */
	mtdcr (memcfga, mem_rtr);
	mtdcr (memcfgd, tmp);

	/* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
	mtdcr (memcfga, mem_mcopt1);
	tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80E00000;
	mtdcr (memcfga, mem_mcopt1);
	mtdcr (memcfgd, tmp);


   /*-------------------------------------------------------------------------+
   | Interrupt controller setup for the PIP405 board.
   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
   |       IRQ 16    405GP internally generated; active low; level sensitive
   |       IRQ 17-24 RESERVED
   |       IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive
   |       IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
   |       IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
   | Note for PIP405 board:
   |       An interrupt taken for the SouthBridge (IRQ 25) indicates that
   |       the Interrupt Controller in the South Bridge has caused the
   |       interrupt. The IC must be read to determine which device
   |       caused the interrupt.
   |
   +-------------------------------------------------------------------------*/
	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */
	mtdcr (uicer, 0x00000000);	/* disable all ints */
	mtdcr (uiccr, 0x00000000);	/* set all to be non-critical (for now) */
	mtdcr (uicpr, 0xFFFFFF80);	/* set int polarities */
	mtdcr (uictr, 0x10000000);	/* set int trigger levels */
	mtdcr (uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
	mtdcr (uicsr, 0xFFFFFFFF);	/* clear all ints */

	return 0;
}


/* ------------------------------------------------------------------------- */

/*
 * Check Board Identity:
 */

int checkboard (void)
{
	unsigned char s[50];
	unsigned char bc;
	int i;
	backup_t *b = (backup_t *) s;

	puts ("Board: ");

	i = getenv_r ("serial#", s, 32);
	if ((i == 0) || strncmp (s, "PIP405", 6)) {
		get_backup_values (b);
		if (strncmp (b->signature, "MPL\0", 4) != 0) {
			puts ("### No HW ID - assuming PIP405");
		} else {
			b->serial_name[6] = 0;
			printf ("%s SN: %s", b->serial_name,
				&b->serial_name[7]);
		}
	} else {
		s[6] = 0;
		printf ("%s SN: %s", s, &s[7]);
	}
	bc = in8 (CONFIG_PORT_ADDR);
	printf (" Boot Config: 0x%x\n", bc);
	return (0);
}


/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
/*
  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
  the necessary info for SDRAM controller configuration
*/
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
static int test_dram (unsigned long ramsize);

long int initdram (int board_type)
{
	DECLARE_GLOBAL_DATA_PTR;

	unsigned long bank_reg[4], tmp, bank_size;
	int i, ds;
	unsigned long TotalSize;

	ds = 0;
	/* since the DRAM controller is allready set up,
	 * calculate the size with the bank registers
	 */
	mtdcr (memcfga, mem_mb0cf);
	bank_reg[0] = mfdcr (memcfgd);
	mtdcr (memcfga, mem_mb1cf);
	bank_reg[1] = mfdcr (memcfgd);
	mtdcr (memcfga, mem_mb2cf);
	bank_reg[2] = mfdcr (memcfgd);
	mtdcr (memcfga, mem_mb3cf);
	bank_reg[3] = mfdcr (memcfgd);
	TotalSize = 0;
	for (i = 0; i < 4; i++) {
		if ((bank_reg[i] & 0x1) == 0x1) {
			tmp = (bank_reg[i] >> 17) & 0x7;
			bank_size = 4 << tmp;
			TotalSize += bank_size;
		} else
			ds = 1;
	}
	if (ds == 1)
		printf ("single-sided DIMM ");
	else
		printf ("double-sided DIMM ");
	test_dram (TotalSize * 1024 * 1024);
	/* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */
	(void) get_clocks();
	if (gd->cpu_clk > 220000000)
		TotalSize /= 2;
	return (TotalSize * 1024 * 1024);
}

/* ------------------------------------------------------------------------- */


static int test_dram (unsigned long ramsize)
{
	/* not yet implemented */
	return (1);
}


extern flash_info_t flash_info[];	/* info for FLASH chips */

int misc_init_r (void)
{
	DECLARE_GLOBAL_DATA_PTR;
	/* adjust flash start and size as well as the offset */
	gd->bd->bi_flashstart=0-flash_info[0].size;
	gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
	gd->bd->bi_flashoffset=0;

	/* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
	if (mfdcr(strap) & PSR_ROM_LOC)
	       mtspr(ccr0, (mfspr(ccr0) & ~0x80));

	return (0);
}

/***************************************************************************
 * some helping routines
 */

int overwrite_console (void)
{
	return (in8 (CONFIG_PORT_ADDR) & 0x1);	/* return TRUE if console should be overwritten */
}


extern int isa_init (void);


void print_pip405_rev (void)
{
	unsigned char part, vers, cfg;

	part = in8 (PLD_PART_REG);
	vers = in8 (PLD_VERS_REG);
	cfg = in8 (PLD_BOARD_CFG_REG);
	printf ("Rev:   PIP405-%d Rev %c PLD%d %d PLD%d %d\n",
			16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf,
			vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf);
}

extern void check_env(void);


int last_stage_init (void)
{
	print_pip405_rev ();
	isa_init ();
	show_stdio_dev ();
	check_env();
	return 0;
}

/************************************************************************
* Print PIP405 Info
************************************************************************/
void print_pip405_info (void)
{
	unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr,
			compwr, nicvga, scsirst;

	part = in8 (PLD_PART_REG);
	vers = in8 (PLD_VERS_REG);
	cfg = in8 (PLD_BOARD_CFG_REG);
	ledu = in8 (PLD_LED_USER_REG);
	sysman = in8 (PLD_SYS_MAN_REG);
	flashcom = in8 (PLD_FLASH_COM_REG);
	can = in8 (PLD_CAN_REG);
	serpwr = in8 (PLD_SER_PWR_REG);
	compwr = in8 (PLD_COM_PWR_REG);
	nicvga = in8 (PLD_NIC_VGA_REG);
	scsirst = in8 (PLD_SCSI_RST_REG);
	printf ("PLD Part %d version %d\n",
		part & 0xf, vers & 0xf);
	printf ("PLD Part %d version %d\n",
		(part >> 4) & 0xf, (vers >> 4) & 0xf);
	printf ("Board Revision %c\n", (cfg & 0xf) + 'A');
	printf ("Population Options %d %d %d %d\n",
		(cfg >> 4) & 0x1, (cfg >> 5) & 0x1,
		(cfg >> 6) & 0x1, (cfg >> 7) & 0x1);
	printf ("User LED0 %s User LED1 %s\n",
		((ledu & 0x1) == 0x1) ? "on" : "off",
		((ledu & 0x2) == 0x2) ? "on" : "off");
	printf ("Additionally Options %d %d\n",
		(ledu >> 2) & 0x1, (ledu >> 3) & 0x1);
	printf ("User Config Switch %d %d %d %d\n",
		(ledu >> 4) & 0x1, (ledu >> 5) & 0x1,
		(ledu >> 6) & 0x1, (ledu >> 7) & 0x1);
	switch (sysman & 0x3) {
	case 0:
		printf ("PCI Clocks are running\n");
		break;
	case 1:
		printf ("PCI Clocks are stopped in POS State\n");
		break;
	case 2:
		printf ("PCI Clocks are stopped when PCI_STP# is asserted\n");
		break;
	case 3:
		printf ("PCI Clocks are stopped\n");
		break;
	}
	switch ((sysman >> 2) & 0x3) {
	case 0:
		printf ("Main Clocks are running\n");
		break;
	case 1:
		printf ("Main Clocks are stopped in POS State\n");
		break;
	case 2:
	case 3:
		printf ("PCI Clocks are stopped\n");
		break;
	}
	printf ("INIT asserts %sINT2# (SMI)\n",
			((sysman & 0x10) == 0x10) ? "" : "not ");
	printf ("INIT asserts %sINT1# (NMI)\n",
			((sysman & 0x20) == 0x20) ? "" : "not ");
	printf ("INIT occured %d\n", (sysman >> 6) & 0x1);
	printf ("SER1 is routed to %s\n",
			((flashcom & 0x1) == 0x1) ? "RS485" : "RS232");
	printf ("COM2 is routed to %s\n",
			((flashcom & 0x2) == 0x2) ? "RS485" : "RS232");
	printf ("RS485 is configured as %s duplex\n",
			((flashcom & 0x4) == 0x4) ? "full" : "half");
	printf ("RS485 is connected to %s\n",
			((flashcom & 0x8) == 0x8) ? "COM1" : "COM2");
	printf ("SER1 uses handshakes %s\n",
			((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS");
	printf ("Bootflash is %swriteprotected\n",
			((flashcom & 0x20) == 0x20) ? "not " : "");
	printf ("Bootflash VPP is %s\n",
			((flashcom & 0x40) == 0x40) ? "on" : "off");
	printf ("Bootsector is %swriteprotected\n",
			((flashcom & 0x80) == 0x80) ? "not " : "");
	switch ((can) & 0x3) {
	case 0:
		printf ("CAN Controller is on address 0x1000..0x10FF\n");
		break;
	case 1:
		printf ("CAN Controller is on address 0x8000..0x80FF\n");
		break;
	case 2:
		printf ("CAN Controller is on address 0xE000..0xE0FF\n");
		break;
	case 3:
		printf ("CAN Controller is disabled\n");
		break;
	}
	switch ((can >> 2) & 0x3) {
	case 0:
		printf ("CAN Controller Reset is ISA Reset\n");
		break;
	case 1:
		printf ("CAN Controller Reset is ISA Reset and POS State\n");
		break;
	case 2:
	case 3:
		printf ("CAN Controller is in reset\n");
		break;
	}
	if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13))
		printf ("CAN Interrupt is disabled\n");
	else
		printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf);
	switch (serpwr & 0x3) {
	case 0:
		printf ("SER0 Drivers are enabled\n");
		break;
	case 1:
		printf ("SER0 Drivers are disabled in the POS state\n");
		break;
	case 2:
	case 3:
		printf ("SER0 Drivers are disabled\n");
		break;
	}
	switch ((serpwr >> 2) & 0x3) {
	case 0:
		printf ("SER1 Drivers are enabled\n");
		break;
	case 1:
		printf ("SER1 Drivers are disabled in the POS state\n");
		break;
	case 2:
	case 3:
		printf ("SER1 Drivers are disabled\n");
		break;
	}
	switch (compwr & 0x3) {
	case 0:
		printf ("COM1 Drivers are enabled\n");
		break;
	case 1:
		printf ("COM1 Drivers are disabled in the POS state\n");
		break;
	case 2:
	case 3:
		printf ("COM1 Drivers are disabled\n");
		break;
	}
	switch ((compwr >> 2) & 0x3) {
	case 0:
		printf ("COM2 Drivers are enabled\n");
		break;
	case 1:
		printf ("COM2 Drivers are disabled in the POS state\n");
		break;
	case 2:
	case 3:
		printf ("COM2 Drivers are disabled\n");
		break;
	}
	switch ((nicvga) & 0x3) {
	case 0:
		printf ("PHY is running\n");
		break;
	case 1:
		printf ("PHY is in Power save mode in POS state\n");
		break;
	case 2:
	case 3:
		printf ("PHY is in Power save mode\n");
		break;
	}
	switch ((nicvga >> 2) & 0x3) {
	case 0:
		printf ("VGA is running\n");
		break;
	case 1:
		printf ("VGA is in Power save mode in POS state\n");
		break;
	case 2:
	case 3:
		printf ("VGA is in Power save mode\n");
		break;
	}
	printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not ");
	printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not ");
	printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1,
			(nicvga >> 7) & 0x1);
	switch ((scsirst) & 0x3) {
	case 0:
		printf ("SCSI Controller is running\n");
		break;
	case 1:
		printf ("SCSI Controller is in Power save mode in POS state\n");
		break;
	case 2:
	case 3:
		printf ("SCSI Controller is in Power save mode\n");
		break;
	}
	printf ("SCSI termination is %s\n",
			((scsirst & 0x4) == 0x4) ? "disabled" : "enabled");
	printf ("SCSI Controller is %sreseted\n",
			((scsirst & 0x10) == 0x10) ? "" : "not ");
	printf ("IDE disks are %sreseted\n",
			((scsirst & 0x20) == 0x20) ? "" : "not ");
	printf ("ISA Bus is %sreseted\n",
			((scsirst & 0x40) == 0x40) ? "" : "not ");
	printf ("Super IO is %sreseted\n",
			((scsirst & 0x80) == 0x80) ? "" : "not ");
}

void user_led0 (unsigned char on)
{
	if (on == TRUE)
		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1));
	else
		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe));
}

void user_led1 (unsigned char on)
{
	if (on == TRUE)
		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2));
	else
		out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd));
}

void ide_set_reset (int idereset)
{
	/* if reset = 1 IDE reset will be asserted */
	unsigned char resreg;

	resreg = in8 (PLD_SCSI_RST_REG);
	if (idereset == 1)
		resreg |= 0x20;
	else {
		udelay(10000);
		resreg &= 0xdf;
	}
	out8 (PLD_SCSI_RST_REG, resreg);
}