📄 measure_temp.lst
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01B2 0000 NOP
01B3 0000 NOP
(0164) PORTF &=0xfb;//SCK=0;
01B4 91800062 LDS R24,0x62
01B6 7F8B ANDI R24,0xFB
01B7 93800062 STS 0x62,R24
(0165) DATA_TO_1();
01B9 91800062 LDS R24,0x62
01BB 6082 ORI R24,2
01BC 93800062 STS 0x62,R24
(0166) if(error >0)
01BE E080 LDI R24,0
01BF 1784 CP R24,R20
01C0 F408 BCC 0x01C2
(0167) PORTA |=0x04;
01C1 9ADA SBI 0x1B,2
(0168) return error; //error=1 in case of no acknowledge
01C2 2D0A MOV R16,R10
01C3 940E040E CALL pop_xgset5
01C5 9508 RET
_s_read_byte:
val --> R10
i --> R20
ack --> R16
01C6 940E042A CALL push_xgsetx
(0169) }
(0170) char s_read_byte(unsigned char ack)
(0171) //----------------------------------------------------------------------------------
(0172) // reads a byte form the Sensibus and gives an acknowledge in case of "ack=1"
(0173) {
(0174) unsigned char i,val=0;
01C8 24AA CLR R10
(0175) //DDRF |=0x04;
(0176) //DDRF &=0xfd;
(0177) PORTF |=0x02;//DATA=1;
01C9 91800062 LDS R24,0x62
01CB 6082 ORI R24,2
01CC 93800062 STS 0x62,R24
(0178) _NOP();_NOP();_NOP();
01CE 0000 NOP
01CF 0000 NOP
01D0 0000 NOP
(0179) //release DATA-line
(0180) //for (i=0x80;i>0;i/=2)
(0181) i=0x80; //shift bit for masking
01D1 E840 LDI R20,0x80
(0182) { PORTF |=0x04;//SCK=1;
01D2 91800062 LDS R24,0x62
01D4 6084 ORI R24,4
01D5 93800062 STS 0x62,R24
(0183) _NOP(); //clk for SENSI-BUS
01D7 0000 NOP
(0184) if (PINF&0x02) val=(val | i); //read bit
01D8 B180 IN R24,0x00
01D9 7082 ANDI R24,2
01DA F009 BEQ 0x01DC
01DB 2AA4 OR R10,R20
(0185) PORTF &=0xfb;//SCK=0;
01DC 91800062 LDS R24,0x62
01DE 7F8B ANDI R24,0xFB
01DF 93800062 STS 0x62,R24
(0186) _NOP();
01E1 0000 NOP
(0187) }
(0188) i=0x40;
01E2 E440 LDI R20,0x40
(0189) { PORTF |=0x04;//SCK=1;
01E3 91800062 LDS R24,0x62
01E5 6084 ORI R24,4
01E6 93800062 STS 0x62,R24
(0190) _NOP(); //clk for SENSI-BUS
01E8 0000 NOP
(0191) if (PINF&0x02) val=(val | i); //read bit
01E9 B180 IN R24,0x00
01EA 7082 ANDI R24,2
01EB F009 BEQ 0x01ED
01EC 2AA4 OR R10,R20
(0192) PORTF &=0xfb;//SCK=0;
01ED 91800062 LDS R24,0x62
01EF 7F8B ANDI R24,0xFB
01F0 93800062 STS 0x62,R24
(0193) _NOP();
01F2 0000 NOP
(0194) }
(0195) i=0x20;
01F3 E240 LDI R20,0x20
(0196) { PORTF |=0x04;//SCK=1;
01F4 91800062 LDS R24,0x62
01F6 6084 ORI R24,4
01F7 93800062 STS 0x62,R24
(0197) _NOP(); //clk for SENSI-BUS
01F9 0000 NOP
(0198) if (PINF&0x02) val=(val | i); //read bit
01FA B180 IN R24,0x00
01FB 7082 ANDI R24,2
01FC F009 BEQ 0x01FE
01FD 2AA4 OR R10,R20
(0199) PORTF &=0xfb;//SCK=0;
01FE 91800062 LDS R24,0x62
0200 7F8B ANDI R24,0xFB
0201 93800062 STS 0x62,R24
(0200) _NOP();
0203 0000 NOP
(0201) }
(0202) i=0x10;
0204 E140 LDI R20,0x10
(0203) { PORTF |=0x04;//SCK=1;
0205 91800062 LDS R24,0x62
0207 6084 ORI R24,4
0208 93800062 STS 0x62,R24
(0204) _NOP(); //clk for SENSI-BUS
020A 0000 NOP
(0205) if (PINF&0x02) val=(val | i); //read bit
020B B180 IN R24,0x00
020C 7082 ANDI R24,2
020D F009 BEQ 0x020F
020E 2AA4 OR R10,R20
(0206) PORTF &=0xfb;//SCK=0;
020F 91800062 LDS R24,0x62
0211 7F8B ANDI R24,0xFB
0212 93800062 STS 0x62,R24
(0207) _NOP();
0214 0000 NOP
(0208) }
(0209) i=0x08;
0215 E048 LDI R20,0x8
(0210) { PORTF |=0x04;//SCK=1;
0216 91800062 LDS R24,0x62
0218 6084 ORI R24,4
0219 93800062 STS 0x62,R24
(0211) _NOP(); //clk for SENSI-BUS
021B 0000 NOP
(0212) if (PINF&0x02) val=(val | i); //read bit
021C B180 IN R24,0x00
021D 7082 ANDI R24,2
021E F009 BEQ 0x0220
021F 2AA4 OR R10,R20
(0213) PORTF &=0xfb;//SCK=0;
0220 91800062 LDS R24,0x62
0222 7F8B ANDI R24,0xFB
0223 93800062 STS 0x62,R24
(0214) _NOP();
0225 0000 NOP
(0215) }
(0216) i=0x04;
0226 E044 LDI R20,4
(0217) { PORTF |=0x04;//SCK=1;
0227 91800062 LDS R24,0x62
0229 6084 ORI R24,4
022A 93800062 STS 0x62,R24
(0218) _NOP(); //clk for SENSI-BUS
022C 0000 NOP
(0219) if (PINF&0x02) val=(val | i); //read bit
022D B180 IN R24,0x00
022E 7082 ANDI R24,2
022F F009 BEQ 0x0231
0230 2AA4 OR R10,R20
(0220) PORTF &=0xfb;//SCK=0;
0231 91800062 LDS R24,0x62
0233 7F8B ANDI R24,0xFB
0234 93800062 STS 0x62,R24
(0221) _NOP();
0236 0000 NOP
(0222) }
(0223) i=0x02;
0237 E042 LDI R20,2
(0224) { PORTF |=0x04;//SCK=1;
0238 91800062 LDS R24,0x62
023A 6084 ORI R24,4
023B 93800062 STS 0x62,R24
(0225) _NOP(); //clk for SENSI-BUS
023D 0000 NOP
(0226) if (PINF&0x02) val=(val | i); //read bit
023E B180 IN R24,0x00
023F 7082 ANDI R24,2
0240 F009 BEQ 0x0242
0241 2AA4 OR R10,R20
(0227) PORTF &=0xfb;//SCK=0;
0242 91800062 LDS R24,0x62
0244 7F8B ANDI R24,0xFB
0245 93800062 STS 0x62,R24
(0228) _NOP();
0247 0000 NOP
(0229) }
(0230) i=0x01;
0248 E041 LDI R20,1
(0231) { PORTF |=0x04;//SCK=1;
0249 91800062 LDS R24,0x62
024B 6084 ORI R24,4
024C 93800062 STS 0x62,R24
(0232) _NOP(); //clk for SENSI-BUS
024E 0000 NOP
(0233) if (PINF&0x02) val=(val | i); //read bit
024F B180 IN R24,0x00
0250 7082 ANDI R24,2
0251 F009 BEQ 0x0253
0252 2AA4 OR R10,R20
(0234) PORTF &=0xfb;//SCK=0;
0253 91800062 LDS R24,0x62
0255 7F8B ANDI R24,0xFB
0256 93800062 STS 0x62,R24
(0235) _NOP();
0258 0000 NOP
(0236) }
(0237) DDRF |=0x02;
0259 91800061 LDS R24,0x61
025B 6082 ORI R24,2
025C 93800061 STS 0x61,R24
(0238) if(ack==0)
025E 2300 TST R16
025F F439 BNE 0x0267
(0239) {PORTF |=0x02;
0260 91800062 LDS R24,0x62
0262 6082 ORI R24,2
0263 93800062 STS 0x62,R24
(0240) _NOP();
0265 0000 NOP
(0241) }
0266 C006 RJMP 0x026D
(0242) else
(0243) {PORTF &=0xfd;
0267 91800062 LDS R24,0x62
0269 7F8D ANDI R24,0xFD
026A 93800062 STS 0x62,R24
(0244) _NOP();
026C 0000 NOP
(0245) }
(0246) //DATA=!ack; //in case of "ack==1" pull down DATA-Line
(0247) PORTF |=0x04;//SCK=1; //clk #9 for ack
026D 91800062 LDS R24,0x62
026F 6084 ORI R24,4
0270 93800062 STS 0x62,R24
(0248) _NOP();_NOP();_NOP();
0272 0000 NOP
0273 0000 NOP
0274 0000 NOP
(0249) //pulswith approx. 5 us
(0250) PORTF &=0xfb;//SCK=0;
0275 91800062 LDS R24,0x62
0277 7F8B ANDI R24,0xFB
0278 93800062 STS 0x62,R24
(0251) _NOP();_NOP();_NOP();
027A 0000 NOP
027B 0000 NOP
027C 0000 NOP
(0252)
(0253) PORTF |=0x02;//DATA=1;
027D 91800062 LDS R24,0x62
027F 6082 ORI R24,2
0280 93800062 STS 0x62,R24
(0254) DDRF &=0xfd;
0282 91800061 LDS R24,0x61
0284 7F8D ANDI R24,0xFD
0285 93800061 STS 0x61,R24
(0255) _NOP(); //release DATA-line
0287 0000 NOP
(0256) return val;
0288 2D0A MOV R16,R10
0289 940E042F CALL pop_xgsetx
028B 9508 RET
(0257) }
(0258)
(0259) void s_transstart(void)
(0260) //----------------------------------------------------------------------------------
(0261) // generates a transmission start
(0262) // _____ ________
(0263) // DATA: |_______|
(0264) // ___ ___
(0265) // SCK : ___| |___| |______
(0266) {
(0267) DATA_TO_1();
_s_transstart:
028C 91800062 LDS R24,0x62
028E 6082 ORI R24,2
028F 93800062 STS 0x62,R24
(0268) _NOP();
0291 0000 NOP
(0269) SCK_TO_0(); //Initial state
0292 91800062 LDS R24,0x62
0294 7F8B ANDI R24,0xFB
0295 93800062 STS 0x62,R24
(0270) _NOP();
0297 0000 NOP
(0271) SCK_TO_1();
0298 91800062 LDS R24,0x62
029A 6084 ORI R24,4
029B 93800062 STS 0x62,R24
(0272) _NOP();
029D 0000 NOP
(0273) DATA_TO_0();
029E 91800062 LDS R24,0x62
02A0 7F8D ANDI R24,0xFD
02A1 93800062 STS 0x62,R24
(0274) _NOP();
02A3 0000 NOP
(0275) SCK_TO_0();
02A4 91800062 LDS R24,0x62
02A6 7F8B ANDI R24,0xFB
02A7 93800062 STS 0x62,R24
(0276) //delay_us(5); //pulswith approx. 5 us
(0277) _NOP();
02A9 0000 NOP
(0278) _NOP();
02AA 0000 NOP
(0279) _NOP();
02AB 0000 NOP
(0280) _NOP();
02AC 0000 NOP
(0281) _NOP();
02AD 0000 NOP
(0282) SCK_TO_1();
02AE 91800062 LDS R24,0x62
02B0 6084 ORI R24,4
02B1 93800062 STS 0x62,R24
(0283) _NOP();
02B3 0000 NOP
(0284) DATA_TO_1();
02B4 91800062 LDS R24,0x62
02B6 6082 ORI R24,2
02B7 93800062 STS 0x62,R24
(0285) _NOP();
02B9 0000 NOP
(0286) SCK_TO_0();
02BA 91800062 LDS R24,0x62
02BC 7F8B ANDI R24,0xFB
02BD 93800062 STS 0x62,R24
(0287) _NOP();
02BF 0000 NOP
02C0 9508 RET
_s_connectionreset:
i --> R20
02C1 934A ST R20,-Y
02C2 935A ST R21,-Y
(0288) }
(0289)
(0290)
(0291) void s_connectionreset(void)
(0292) //----------------------------------------------------------------------------------
(0293) // communication reset: DATA-line=1 and at least 9 SCK cycles followed by transstart
(0294) // _____________________________________________________ ________
(0295) // DATA: |_______|
(0296) // _ _ _ _ _ _ _ _ _ ___ ___
(0297) // SCK : __| |__| |__| |__| |__| |__| |__| |__| |__| |______| |___| |______
(0298) {
(0299) unsigned char i;
(0300) DATA_TO_1();
02C3 91800062 LDS R24,0x62
02C5 6082 ORI R24,2
02C6 93800062 STS 0x62,R24
(0301) _NOP();
02C8 0000 NOP
(0302) SCK_TO_0(); //Initial state
02C9 91800062 LDS R24,0x62
02CB 7F8B ANDI R24,0xFB
02CC 93800062 STS 0x62,R24
(0303) _NOP();
02CE 0000 NOP
(0304) for(i=0;i<9;i++) //9 SCK cycles
02CF 2744 CLR R20
02D0 C00D RJMP 0x02DE
(0305) { SCK_TO_1();
02D1 91800062 LDS R24,0x62
02D3 6084 ORI R24,4
02D4 93800062 STS 0x62,R24
(0306) _NOP();
02D6 0000 NOP
(0307) SCK_TO_0();
02D7 91800062 LDS R24,0x62
02D9 7F8B ANDI R24,0xFB
02DA 93800062 STS 0x62,R24
(0308) _NOP();
02DC 0000 NOP
02DD 9543 INC R20
02DE 3049 CPI R20,0x9
02DF F388 BCS 0x02D1
(0309) }
(0310) s_transstart(); //transmission start
02E0 DFAB RCALL _s_transstart
02E1 9159 LD R21,Y+
02E2 9149 LD R20,Y+
02E3 9508 RET
_s_measure:
error --> R20
k --> R12
i --> R14
j --> R22
mode --> R12
p_checksum --> R10
02E4 940E0403 CALL push_xgset5
02E6 2EC2 MOV R12,R18
02E7 0158 MOVW R10,R16
(0311) }
(0312)
(0313)
(0314) char s_measure(unsigned char *p_checksum, unsigned char mode)
(0315) //----------------------------------------------------------------------------------
(0316) // makes a measurement (humidity/temperature) with checksum
(0317) {
(0318) unsigned error=0;
02E8 2744 CLR R20
02E9 2755 CLR R21
(0319) unsigned int i,j,k;
(0320)
(0321) s_transstart(); //transmission start
02EA DFA1 RCALL _s_transstart
(0322) switch(mode){ //send command to sensor
02EB 24DD CLR R13
02EC 20CC TST R12
02ED F411 BNE 0x02F0
02EE 20DD TST R13
02EF F031 BEQ 0x02F6
02F0 01C6 MOVW R24,R12
02F1 3081 CPI R24,1
02F2 E0E0 LDI R30,0
02F3 079E CPC R25,R30
02F4 F041 BEQ 0x02FD
02F5 C00D RJMP 0x0303
(0323) case TEMP : error+=s_write_byte(MEASURE_TEMP); break;
02F6 E003 LDI R16,3
02F7 DD96 RCALL _s_write_byte
02F8 2E20 MOV R2,R16
02F9 2433 CLR R3
02FA 0D42 ADD R20,R2
02FB 1D53 ADC R21,R3
02FC C006 RJMP 0x0303
(0324) case HUMI : error+=s_write_byte(MEASURE_HUMI); break;
02FD E005 LDI R16,5
02FE DD8F RCALL _s_write_byte
02FF 2E20 MOV R2,R16
0300 2433 CLR R3
0301 0D42 ADD R20,R2
0302 1D53 ADC R21,R3
(0325) default : break;
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