sysinit.c

用来测试mcf5249的嵌入式测试程序

/*
 * File:		sysinit.c
 * Purpose:		Power-on Reset configuration of the MCF5249.
 *
 */

#include "type.h"
#include "mcf5249.h"
#include "base.h"
#include "sysinit.h"

/********************************************************************/
void mcf5249_init(void)
{
	/*******************************************************
	*	This routine to initialize the MCF5249 modules for the  
	*	(M5249AN | M5249C3) board. A temporary stack has been
	*	 setup in the internal SRAM.
	********************************************************/
	mcf5249_sim_init();
	mcf5249_timer_init();
	mcf5249_uart_init();
	mcf5249_mbus_init();
	mcf5249_dma_init();
	mcf5249_cs_init();
	mcf5249_sdram_init();
	
	/* Enable level 7 interrupt to ColdFire core */
	imm->sim.IMR &= ~MCF5249_SIM_IMR_EINT7;

	/*
	switch (imm->sim.RSR)
	{
		case MCF5249_SIM_RSR_HRST:
			asm(nop);    //Hard Reset
			break;
		case MCF5249_SIM_RSR_SWTR:
			asm(nop);    //Software Watchdog Reset
			break;
	}
	imm->sim.RSR = (0
		| MCF5249_SIM_RSR_HRST
		| MCF5249_SIM_RSR_SWTR
		) ;
	*/
	mcf5249_gpio_init();
	mcf5249_ide_init();
	mcf5249_iis_init();
	mcf5249_qspi_init();
}

/****************************************************************/
void mcf5249_sim_init(void)
{
	/*******************************************************
	*
	* This routine executed upon reset to initialize
	* MCF5249 periphs.  An initial stack must have been setup
	* in the SRAM in order for this routine to work.
	*
	*******************************************************/

	imm->sim.SYPCR	=  0;	/*  Disable the Software Watchdog */
	imm->sim.MARBCR	=  0;	/*  Disable external visibility of internal bus */
	imm->sim.IMR	=  0xFFFFFFFF;	/*  Mask all interrupt sources */
	imm->sim.AVCR	=  0xFF;	/*  Autovector all external interrupts */
 
	/*
	 * Setup Interrupt Source Vectors
	 */
	imm->sim.ICR0 = ( 0                     /* Software Watchdog */
			| MCF5249_SIM_ICR_AVEC
			| MCF5249_SIM_ICR_IL(7)
			| MCF5249_SIM_ICR_IP_EXT ) ;
	imm->sim.ICR1 = ( 0
			| MCF5249_SIM_ICR_AVEC          /* Timer 1 */
			| MCF5249_SIM_ICR_IL(6)
			//| MCF5249_SIM_ICR_IP_EXT
			| MCF5249_SIM_ICR_IP_INT ) ;
	imm->sim.ICR2 = ( 0
			| MCF5249_SIM_ICR_AVEC          /* Timer 2 */
			| MCF5249_SIM_ICR_IL(5)
			| MCF5249_SIM_ICR_IP_INT ) ;
	imm->sim.ICR3 = ( 0
			| MCF5249_SIM_ICR_AVEC          /* MBUS    */
			| MCF5249_SIM_ICR_IL(3) ) ;
	imm->sim.ICR4 = ( 0
			| MCF5249_SIM_ICR_AVEC          /* UART 1  */
			| MCF5249_SIM_ICR_IL(3)
			| MCF5249_SIM_ICR_IP_EXT ) ;
	imm->sim.ICR5 = ( 0
			| MCF5249_SIM_ICR_AVEC          /* UART 2  */
			| MCF5249_SIM_ICR_IL(3)
			| MCF5249_SIM_ICR_IP_INT ) ;
	imm->sim.ICR6 = ( 0
			| MCF5249_SIM_ICR_AVEC          /* DMA 0   */
			| MCF5249_SIM_ICR_IL(2) ) ;
	imm->sim.ICR7 = ( 0
			| MCF5249_SIM_ICR_AVEC          /* DMA 1   */
			| MCF5249_SIM_ICR_IL(2)
			| MCF5249_SIM_ICR_IP_INT ) ;
	imm->sim.ICR8 = ( 0
			| MCF5249_SIM_ICR_AVEC          /* DMA 2   */
			| MCF5249_SIM_ICR_IL(2)
			| MCF5249_SIM_ICR_IP_EXT ) ;
	imm->sim.ICR9 = ( 0
			| MCF5249_SIM_ICR_AVEC          /* DMA 3   */
			| MCF5249_SIM_ICR_IL(2)
			| MCF5249_SIM_ICR_IP_EXT
			| MCF5249_SIM_ICR_IP_INT ) ;
	imm->sim.ICR10 = ( 0
			| MCF5249_SIM_ICR_AVEC          /* QSPI    */
			| MCF5249_SIM_ICR_IL(1) ) ;
	imm->sim.ICR11 = ( 0
			| MCF5249_SIM_ICR_AVEC          /* unused  */
			| MCF5249_SIM_ICR_IL(1)
			| MCF5249_SIM_ICR_IP_EXT ) ;
			
	imm2->sint.INTPRI1 = 0x00007000;
	imm2->sint.INTPRI2 = 0;
	imm2->sint.INTPRI3 = 0;
	imm2->sint.INTPRI4 = 0;
	imm2->sint.INTPRI5 = 0x00700000;
	imm2->sint.INTPRI6 = 0;
	imm2->sint.INTPRI7 = 0;
	imm2->sint.INTPRI8 = 0;
	imm2->sint.INTBASE = 0x80;
}

/****************************************************************/
void mcf5249_mbus_init(void)
{
	imm->mbus.MBCR = 0;     /* Disable MBUS */ 
    imm2->iic2.MBCR2 = 0;
}

/****************************************************************/
void mcf5249_dma_init(void)
{
	imm->dma.DCR0 = 0;	/* Disable DMA 0 */
	imm->dma.DCR1 = 0;	/* Disable DMA 1 */
	imm->dma.DCR2 = 0;	/* Disable DMA 2 */
	imm->dma.DCR3 = 0;	/* Disable DMA 3 */
}

/****************************************************************/
//Set 50ms
void mcf5249_timer_init(void)
{
	/*	Reset timers and disable them */
	//imm->timer.TMR0 = 0x041a;           //Master system clock/(4+1)
	imm->timer.TMR0 = 0x311a;           //Master system clock/(49+1)
	imm->timer.TMR1 = 0;
	imm->timer.TER0 = ( 0
		| MCF5249_TIMER_TER_REF
		| MCF5249_TIMER_TER_CAP
		) ;
	imm->timer.TER1 = ( 0
		| MCF5249_TIMER_TER_REF
		| MCF5249_TIMER_TER_CAP
		) ;
	//imm->timer.TRR0 = 0x0032;           //Reference ->79.968kHz
	imm->timer.TRR0 = 0x4e20;           //Reference ->19.992Hz

	/* Enable Timer0 interrupt to ColdFire core */
	//imm->sim.IMR &= ~MCF5249_SIM_IMR_TIMER1;
	//imm->timer.TMR0 |= MCF5249_TIMER_TMR_RST;
}

/****************************************************************/
void mcf5249_uart_init(void)
{
	/************************************************************************/
	/*  UART 1                                                              */
	/************************************************************************/
	imm->uart1.UCR = MCF5249_UART_UCR_RESET_TX;		/* Transmitter Reset    */
	imm->uart1.UCR = MCF5249_UART_UCR_RESET_RX;		/* Receiver Reset       */
	imm->uart1.UCR = MCF5249_UART_UCR_TX_ENABLED;	/* Enable Transmitter	*/
	imm->uart1.UCR = MCF5249_UART_UCR_RX_ENABLED;	/* Enable Receiver		*/
	imm->uart1.UCR = MCF5249_UART_UCR_RESET_MR;		/* Mode Register Reset  */
 
	imm->uart1.UMR = ( 0
		| MCF5249_UART_UMR1_PM_NONE			/* No parity					*/
		| MCF5249_UART_UMR1_BC_8			/* 8 bits per character			*/
		) ;
	imm->uart1.UMR = ( 0
		| MCF5249_UART_UMR2_CM_NORMAL		/* No echo or loopback			*/
		| MCF5249_UART_UMR2_STOP_BITS_1		/* 1 stop bit					*/
		) ;
	imm->uart1.USR = ( 0
		| MCF5249_UART_UCSR_RCS0
		| MCF5249_UART_UCSR_RCS2
		| MCF5249_UART_UCSR_RCS3
		| MCF5249_UART_UCSR_TCS0
		| MCF5249_UART_UCSR_TCS2
		| MCF5249_UART_UCSR_TCS3
		) ;
	imm->uart1.UIR = 0;						/* Disable all interrupts       */
	imm->uart1.UBG1 = 0;
	imm->uart1.UBG2 = 0x63;					/* Set baud to 19200, 45MHZ		*/

    /************************************************************************/
    /*  UART 2                                                              */
    /************************************************************************/
	imm->uart2.UCR = MCF5249_UART_UCR_RESET_TX;		/* Transmitter Reset    */
	imm->uart2.UCR = MCF5249_UART_UCR_RESET_RX;		/* Receiver Reset       */
	imm->uart2.UCR = MCF5249_UART_UCR_TX_ENABLED;	/* Enable Transmitter	*/
	imm->uart2.UCR = MCF5249_UART_UCR_RX_ENABLED;	/* Enable Receiver		*/
	imm->uart2.UCR = MCF5249_UART_UCR_RESET_MR;		/* Mode Register Reset  */
 
	imm->uart2.UMR = ( 0
		| MCF5249_UART_UMR1_PM_NONE			/* No parity					*/
		| MCF5249_UART_UMR1_BC_8			/* 8 bits per character			*/
		) ;
	imm->uart2.UMR = ( 0
		| MCF5249_UART_UMR2_CM_NORMAL		/* No echo or loopback			*/
		| MCF5249_UART_UMR2_STOP_BITS_1		/* 1 stop bit					*/
		) ;
	imm->uart2.USR = ( 0
		| MCF5249_UART_UCSR_RCS0
		| MCF5249_UART_UCSR_RCS2
		| MCF5249_UART_UCSR_RCS3
		| MCF5249_UART_UCSR_TCS0
		| MCF5249_UART_UCSR_TCS2
		| MCF5249_UART_UCSR_TCS3
		) ;
	imm->uart2.UIR = 0;						/* Disable all interrupts       */
	imm->uart2.UBG1 = 0;
	imm->uart2.UBG2 = 0x63;					/* Set baud to 19200, 45MHZ		*/
}


/****************************************************************/
void mcf5249_cs_init(void)
{
	/*	ChipSelect 0 is the global chip select coming out of system */
	/*	reset.CS0 is asserted for every access until CSMR0 is written. */
	/*	Therefore, the entire ChipSelect must be properly set prior to  */
	/*	asserting CSMR0_V. */
	imm->cs.CSAR0 = MCF5249_CS_CSAR(FLASH_ADDRESS);
	imm->cs.CSCR0 = ( 0
			| MCF5249_CS_CSCR_WS(3)
			| MCF5249_CS_CSCR_AA		/* TA_ generated internally */
			| MCF5249_CS_CSCR_PS_16 );
	imm->cs.CSMR0 = ( 0
			| MCF5249_CS_CSMR_MASK_2M
			| MCF5249_CS_CSMR_CI
			| MCF5249_CS_CSMR_V );

	imm->cs.CSAR1 = MCF5249_CS_CSAR(NET_ADDRESS);
	imm->cs.CSCR1 = ( 0
			| MCF5249_CS_CSCR_WS(3)
			| MCF5249_CS_CSCR_AA		/* TA_ generated internally */
			| MCF5249_CS_CSCR_PS_16 );
	imm->cs.CSMR1 = ( 0
			| MCF5249_CS_CSMR_MASK_2M
			| MCF5249_CS_CSMR_CI
			| MCF5249_CS_CSMR_V );

	imm->cs.CSAR2 = MCF5249_CS_CSAR(IDE_ADDRESS);
	imm->cs.CSCR2 = ( 0
			| MCF5249_CS_CSCR_WS(7)
			| MCF5249_CS_CSCR_AA		/* TA_ generated internally */
			| MCF5249_CS_CSCR_PS_16 );
	imm->cs.CSMR2 = ( 0
			| MCF5249_CS_CSMR_MASK_16M
			| MCF5249_CS_CSMR_CI
			| MCF5249_CS_CSMR_V );
}  

/****************************************************************/
void mcf5249_sdram_init(void)