📄 mcf5249.h
字号:
#define MCF5249_SINT_INTPRI4_INT29 (0x00F00000) /* Interrupt 29 Level */
#define MCF5249_SINT_INTPRI4_INT30 (0x0F000000) /* Interrupt 30 Level */
#define MCF5249_SINT_INTPRI4_INT31 (0xF0000000) /* Interrupt 31 Level */
#define MCF5249_SINT_INTPRI5_INT32 (0x0000000F) /* Interrupt 32 Level */
#define MCF5249_SINT_INTPRI5_INT33 (0x000000F0) /* Interrupt 33 Level */
#define MCF5249_SINT_INTPRI5_INT34 (0x00000F00) /* Interrupt 34 Level */
#define MCF5249_SINT_INTPRI5_INT35 (0x0000F000) /* Interrupt 35 Level */
#define MCF5249_SINT_INTPRI5_INT36 (0x000F0000) /* Interrupt 36 Level */
#define MCF5249_SINT_INTPRI5_INT37 (0x00F00000) /* Interrupt 37 Level */
#define MCF5249_SINT_INTPRI5_INT38 (0x0F000000) /* Interrupt 38 Level */
#define MCF5249_SINT_INTPRI5_INT39 (0xF0000000) /* Interrupt 39 Level */
#define MCF5249_SINT_INTPRI6_INT40 (0x0000000F) /* Interrupt 40 Level */
#define MCF5249_SINT_INTPRI6_INT41 (0x000000F0) /* Interrupt 41 Level */
#define MCF5249_SINT_INTPRI6_INT42 (0x00000F00) /* Interrupt 42 Level */
#define MCF5249_SINT_INTPRI6_INT43 (0x0000F000) /* Interrupt 43 Level */
#define MCF5249_SINT_INTPRI6_INT44 (0x000F0000) /* Interrupt 44 Level */
#define MCF5249_SINT_INTPRI6_INT45 (0x00F00000) /* Interrupt 45 Level */
#define MCF5249_SINT_INTPRI6_INT46 (0x0F000000) /* Interrupt 46 Level */
#define MCF5249_SINT_INTPRI6_INT47 (0xF0000000) /* Interrupt 47 Level */
#define MCF5249_SINT_INTPRI7_INT48 (0x0000000F) /* Interrupt 48 Level */
#define MCF5249_SINT_INTPRI7_INT49 (0x000000F0) /* Interrupt 49 Level */
#define MCF5249_SINT_INTPRI7_INT50 (0x00000F00) /* Interrupt 50 Level */
#define MCF5249_SINT_INTPRI7_INT51 (0x0000F000) /* Interrupt 51 Level */
#define MCF5249_SINT_INTPRI7_INT52 (0x000F0000) /* Interrupt 52 Level */
#define MCF5249_SINT_INTPRI7_INT53 (0x00F00000) /* Interrupt 53 Level */
#define MCF5249_SINT_INTPRI7_INT54 (0x0F000000) /* Interrupt 54 Level */
#define MCF5249_SINT_INTPRI7_INT55 (0xF0000000) /* Interrupt 55 Level */
#define MCF5249_SINT_INTPRI8_INT56 (0x0000000F) /* Interrupt 56 Level */
#define MCF5249_SINT_INTPRI8_INT57 (0x000000F0) /* Interrupt 57 Level */
#define MCF5249_SINT_INTPRI8_INT58 (0x00000F00) /* Interrupt 58 Level */
#define MCF5249_SINT_INTPRI8_INT59 (0x0000F000) /* Interrupt 59 Level */
#define MCF5249_SINT_INTPRI8_INT60 (0x000F0000) /* Interrupt 60 Level */
#define MCF5249_SINT_INTPRI8_INT61 (0x00F00000) /* Interrupt 61 Level */
#define MCF5249_SINT_INTPRI8_INT62 (0x0F000000) /* Interrupt 62 Level */
#define MCF5249_SINT_INTPRI8_INT63 (0xF0000000) /* Interrupt 63 Level */
/***********************************************************************/
/* PLL Registers */
/***********************************************************************/
typedef volatile struct
{
uint8 reserved0[0x180];
uint32 PLLCR; /* PLL Control Register */
} MCF5249_PLL;
//#define MCF5249_PLL_VAL (0x021FC161) // PLLCR -- PLL control register
// CPU clock = 119.952MHz
// AUDIOCLK = Fxtal = 11.2896MHz
// MCLK1 = Fxtal = 11.2896MHz
// MCLK2 = Fxtal = 11.2896MHz
#define MCF5249_PLL_VAL (0x020A8961) // PLLCR -- PLL control register
// CPU clock = 39.984MHz
// AUDIOCLK = Fxtal/2 = 5.6448MHz
// MCLK1 = Fxtal/2 = 5.6448MHz
// MCLK2 = Fxtal/2 = 5.6448MHz
#define MCF5249_PLL_PLLCR_LOCK (0x80000000) /* PLL Lock Falg */
#define MCF5249_PLL_PLLCR_CLSEL (0x70000000) /* MCLK1,MCLK2 Select */
#define MCF5249_PLL_PLLCR_CPUDIV (0x07000000) /* CPU Clock Divider */
#define MCF5249_PLL_PLLCR_CRSEL (0x00800000) /* Input Frequency Select */
#define MCF5249_PLL_PLLCR_AUDIOSEL (0x00400000) /* Audio Clock Select */
#define MCF5249_PLL_PLLCR_DEBUGSEL (0x00200000) /* Debug Select */
#define MCF5249_PLL_PLLCR_VCODIV (0x001FF000) /* VCO Frequency Divider */
#define MCF5249_PLL_PLLCR_QSPISEL (0x00000800) /* QSPI Funtion Select */
#define MCF5249_PLL_PLLCR_RSTSEL (0x00000400) /* RST Funtion Select */
#define MCF5249_PLL_PLLCR_PLLPD (0x00000200) /* PLL Power Down */
#define MCF5249_PLL_PLLCR_PLLDIV (0x000001F0) /* PLL Input Frequency Divider */
#define MCF5249_PLL_PLLCR_VCOOUT (0x0000000C) /* VCO Output Divider */
#define MCF5249_PLL_PLLCR_PLLBP (0x00000001) /* PLL Bypass */
/***********************************************************************/
/* PLL Registers */
/***********************************************************************/
typedef volatile struct
{
uint8 reserved0[0x18C];
uint32 IDECFG1; /* IDE Interface Configuration Register 1 */
uint32 IDECFG2; /* IDE Interface Configuration Register 2 */
} MCF5249_IDE;
#define MCF5249_IDE_CFG1_CS0PRE (0x00000007) /* pre-drive for CS0 */
#define MCF5249_IDE_CFG1_CS0POST (0x00000018) /* post-drive for CS0 */
#define MCF5249_IDE_CFG1_CS1PRE (0x000000E0) /* pre-drive for CS1 */
#define MCF5249_IDE_CFG1_CS1POST (0x00000300) /* post-drive for CS1 */
#define MCF5249_IDE_CFG1_CS2PRE (0x00001C00) /* pre-drive for CS2 */
#define MCF5249_IDE_CFG1_CS2POST (0x00006000) /* post-drive for CS2 */
#define MCF5249_IDE_CFG1_BUFEN1CS1 (0x00010000) /* bufen1 active on CS1 */
#define MCF5249_IDE_CFG1_BUFEN1CS2 (0x00020000) /* bufen1 active on CS2 */
#define MCF5249_IDE_CFG1_BUFEN1CS3 (0x00040000) /* bufen1 active on CS3 */
#define MCF5249_IDE_CFG1_BUFEN2CS1 (0x00080000) /* bufen2 active on CS1 */
#define MCF5249_IDE_CFG1_BUFEN2CS2 (0x00100000) /* bufen2 active on CS2 */
#define MCF5249_IDE_CFG1_BUFEN2CS3 (0x00200000) /* bufen2 active on CS3 */
#define MCF5249_IDE_CFG1_CS3PRE (0x01C00000) /* pre-drive for CS3 */
#define MCF5249_IDE_CFG1_CS3POST (0x06000000) /* post-drive for CS3 */
#define MCF5249_IDE_CFG1_DIOR (0x08000000) /* DIOR active during write cycles */
#define MCF5249_IDE_CFG1_SRE (0x10000000) /* SRE active during write cycles */
#define MCF5249_IDE_CFG2_WAITCNT3 (0x000000FF) /* CS3 delay count */
#define MCF5249_IDE_CFG2_WAITCNT2 (0x0000FF00) /* CS2 delay count */
#define MCF5249_IDE_CFG2_TAEN3 (0x00010000) /* Generate TA for CS3 accesses */
#define MCF5249_IDE_CFG2_IORDYEN3 (0x00020000) /* Allow IORDY to delay TA for CS3 */
#define MCF5249_IDE_CFG2_TAEN2 (0x00040000) /* Generate TA for CS2 accesses */
#define MCF5249_IDE_CFG2_IORDYEN2 (0x00080000) /* Allow IORDY to delay TA for CS2 */
/***********************************************************************/
/* IIC2 Registers */
/***********************************************************************/
typedef volatile struct
{
uint8 reserved0[0x440];
uint8 MADR2; /* M-Bus 2 Address Register */
uint8 reserved1[3];
uint8 MFDR2; /* M-Bus 2 Frequecy Divider Register */
uint8 reserved2[3];
uint8 MBCR2; /* M-Bus 2 Control Register */
uint8 reserved3[3];
uint8 MBSR2; /* M-Bus 2 Status Register */
uint8 reserved4[3];
uint8 MBDR2; /* M-Bus 2 Data I/O Register */
} MCF5249_IIC2;
#define MCF5249_IIC2_MBCR2_IEN (0x80) /* M-Bus 2 Enable bit */
#define MCF5249_IIC2_MBCR2_IIEN (0x40) /* M-Bus 2 Interrupt Enable bit */
#define MCF5249_IIC2_MBCR2_MSTA (0x20) /* M-Bus 2 Master/Slave Select bit */
#define MCF5249_IIC2_MBCR2_MTX (0x10) /* M-Bus 2 Transmit/Receive Mode Select bit */
#define MCF5249_IIC2_MBCR2_TXAK (0x08) /* M-Bus 2 Transmit Acknowledge Enable bit */
#define MCF5249_IIC2_MBCR2_RSTA (0x04) /* M-Bus 2 Repeat Start bit */
#define MCF5249_IIC2_MBSR2_ICF (0x80) /* M-Bus 2 Transfer Flag bit */
#define MCF5249_IIC2_MBSR2_IAAS (0x40) /* M-Bus 2 Own Specific Address bit */
#define MCF5249_IIC2_MBSR2_IBB (0x20) /* M-Bus 2 Bus Busy bit */
#define MCF5249_IIC2_MBSR2_IAL (0x10) /* M-Bus 2 Arbitration Lost bit */
#define MCF5249_IIC2_MBSR2_SRW (0x04) /* M-Bus 2 Slave Transmit/Receive bit */
#define MCF5249_IIC2_MBSR2_IIF (0x02) /* M-Bus 2 Interrupt Flag bit */
#define MCF5249_IIC2_MBSR2_RXAK (0x01) /* M-Bus 2 Receive Acknowledge bit */
/***********************************************************************/
/* IIS Registers */
/***********************************************************************/
typedef volatile struct
{
uint8 reserved0[0x10];
uint32 IIS1CONFIG; /* Config Register for IIS Interface 1 */
uint32 IIS2CONFIG; /* Config Register for IIS Interface 2 */
uint32 IIS3CONFIG; /* Config Register for IIS Interface 3 */
uint32 IIS4CONFIG; /* Config Register for IIS Interface 4 */
uint32 EBU1CONFIG; /* Config Register for EBU Interface 1 */
uint32 EBU1RCVCCHANNEL1; /* Control Channel as Received by EBU1 Interface - first 32 bits */
uint32 EBUTXCCHANNEL1; /* "C" Channel bits for EBU Transmitter Consumer Format */
uint32 EBUTXCCHANNEL2; /* "C" Channel bits for EBU Transmitter Professional Format */
uint32 DATAINCONTROL; /* PDIR Source Select */
//uint32 PDIR1L; /* Processor Data In 1 - Left */
uint32 PDOR1L; /* Processor Data Out 1 - Left */
uint32 reserved1[3];
//uint32 PDIR3L; /* Processor Data In 3 - Left */
uint32 PDOR1R; /* Processor Data Out 1 - Right */
uint32 reserved2[3];
//uint32 PDIR1R; /* Processor Data In 1 - Right */
uint32 PDOR2L; /* Processor Data Out 2 - Left */
uint32 reserved3[3];
//uint32 PDIR3R; /* Processor Data In 3 - Right */
uint32 PDOR2R; /* Processor Data Out 2 - Right */
uint32 reserved4[3];
//uint32 PDIR2; /* Processor Data In 2 - Left + Right */
uint32 PDOR3; /* Processor Data Out 3 - Left + Right */
uint32 reserved5[3];
uint32 UCHANNELTRANSMIT; /* U Channel Transmit Register */
uint32 U1CHANNELRECEIVE; /* U Channel Receive Register First EBU Receiver */
uint32 Q1CHANNELRECEIVE; /* Q Channel Receive Register First EBU Receiver */
uint8 reserved6[2];
uint8 CDTEXTCONTROL; /* CD Text Configuration Register */
uint8 reserved7;
uint32 AUDIOINTERRUPTEN; /* Audio Interrupt Enable Register */
uint32 AUDIOINTERRUPTSTA; /* Audio Interrupt status Register */
uint8 reserved8[50];
uint16 AUDIOGLOB; /* Audio Block New Features */
} MCF5249_IIS;
#define MCF5249_IIS_IISCONFIG_EFCFLG (0x00040000) /* EF/CFLG Insertion Mode bit */
#define MCF5249_IIS_IISCONFIG_CFLG (0x00020000) /* CFLG Sample Position bit */
#define MCF5249_IIS_IISCONFIG_TXSOURCE (0x00010700) /* TX Source Select bit */
#define MCF5249_IIS_IISCONFIG_CLOCKSEL (0x0000f000) /* Clock Select bit */
#define MCF5249_IIS_IISCONFIG_TXFIFO (0x00000800) /* TX FIFO Control bit */
#define MCF5249_IIS_IISCONFIG_SIZE (0x000000c0) /* IIS TX Size bit */
#define MCF5249_IIS_IISCONFIG_MODE (0x00000020) /* IIS and EIAJ Mode Select bit */
#define MCF5249_IIS_IISCONFIG_FLRCK (0x0000001c) /* LRCK Frequency Select bit */
#define MCF5249_IIS_IISCONFIG_LRCK (0x00000002) /* LRCK Invert bit */
#define MCF5249_IIS_IISCONFIG_SCLK (0x00000001) /* SCLK Invert bit */
#define MCF5249_IIS_INT_IIS1TXUNOV (0x80000000) /* IIS1 Transmit Fifo Under/Over bit */
#define MCF5249_IIS_INT_IIS1TXRESYN (0x40000000) /* IIS1 Transmit Fifo Resync bit */
#define MCF5249_IIS_INT_IIS2TXUNOV (0x20000000) /* IIS2 Transmit Fifo Under/Over bit */
#define MCF5249_IIS_INT_IIS2TXRESYN (0x10000000) /* IIS2 Transmit Fifo Resync bit */
#define MCF5249_IIS_INT_EBUTXUNOV (0x08000000) /* EBU Transmit Fifo Under/Over bit */
#define MCF5249_IIS_INT_EBUTXRESYN (0x04000000) /* EBU Transmit Fifo Resync bit */
#define MCF5249_IIS_INT_IEC9581CNEW (0x02000000) /* IEC958-1 Receives new C control Channel Frame bit */
#define MCF5249_IIS_INT_IEC9581NOGOOD (0x01000000) /* IEC958-1 Validity Flag no Good bit */
#define MCF5249_IIS_INT_IEC9581ERROR (0x00800000) /* IEC958-1 Receiver 1 bit or Symbol Error bit */
#define MCF5249_IIS_INT_PDIR3UNOV (0x00400000) /* Processor data in 3 Under/Over bit */
#define MCF5249_IIS_INT_UCHANTXEMPTY (0x00200000) /* U Channel Transmit Register Empty bit */
#define MCF5249_IIS_INT_UCHANTXUNDER (0x00100000) /* U Channel Transmit Register Underrun bit */
#define MCF5249_IIS_INT_UCHANTXNEXT (0x00080000) /* U Channel Transmit Register Next Byte Will be First bit */
#define MCF5249_IIS_INT_IEC9581UQ (0x00040000) /* IEC958-1 U/Q Channel Buffer Full bit */
#define MCF5249_IIS_INT_IEC9582CNEW (0x00020000) /* IEC958-2 Receives new C control Channel Frame bit */
#define MCF5249_IIS_INT_IEC9582NOGOOD (0x00010000) /* IEC958-2 Validity Flag no Good bit */
#define MCF5249_IIS_INT_IEC9582ERROR (0x00008000) /* IEC958-2 Receiver 1 bit or Symbol Error bit */
#define MCF5249_IIS_INT_IEC9582UQ (0x00004000) /* IEC958-2 U/Q Channel Buffer Full bit */
#define MCF5249_IIS_INT_IEC9581UQERROR (0x00002000) /* IEC958 Receiver 1U/Q Channel Error bit */
#define MCF5249_IIS_INT_PDIR1UNOV (0x00001000) /* Processor data in 1 Under/Over bit */
#define MCF5249_IIS_INT_PDIR1RESYN (0x00000800) /* Processor data in 1 Resync bit */
#define MCF5249_IIS_INT_PDIR2UNOV (0x00000400) /* Processor data in 2 Under/Over bit */
#define MCF5249_IIS_INT_PDIR2RESYN (0x00000200) /* Processor data in 2 Resync bit */
#define MCF5249_IIS_INT_AUDIOTICK (0x00000100) /* Audio Tick bit */
#define MCF5249_IIS_INT_IEC9582UQERROR (0x00000080) /* IEC958 Receiver 2U/Q Channel Error bit */
#define MCF5249_IIS_INT_PDIR3RESYN (0x00000040) /* Processor data in 3 Resync bit */
#define MCF5249_IIS_INT_PDIR3FULL (0x00000020) /* Processor data in 3 Full bit */
#define MCF5249_IIS_INT_IIS1TXEMPTY (0x00000010) /* IIS1 Transmit Fifo Empty bit */
#define MCF5249_IIS_INT_IIS2TXEMPTY (0x00000008) /* IIS1 Transmit Fifo Empty bit */
#define MCF5249_IIS_INT_EBUTXEMPTY (0x00000004) /* EBU Transmit Fifo Empty bit */
#define MCF5249_IIS_INT_PDIR2FULL (0x00000002) /* Processor data in 2 Full bit */
#define MCF5249_IIS_INT_PDIR1FULL (0x00000001) /* Processor data in 1 Full bit */
/***********************************************************************/
/* ADC Registers */
/***********************************************************************/
typedef volatile struct
{
uint8 reserved0[0x402];
uint16 ADCONFIG; /* AD Configuration and Status Register */
uint8 reserved1[2];
uint16 ADVALUE; /* AD Measurement Result Register */
} MCF5249_ADC;
#define MCF5249_ADC_ADCONFIG_ADOUT (0x0400) /* TOUT1/GPO35/ADOUT Pin Function Select bit */
#define MCF5249_ADC_ADCONFIG_SOURCE (0x0300) /* AD Input Source Select bits */
#define MCF5249_ADC_ADCONFIG_INTSTA (0x0080) /* AD Interrupt Pending bit */
#define MCF5249_ADC_ADCONFIG_INTEN (0x0040) /* AD Interrupt Enable bit */
#define MCF5249_ADC_ADCONFIG_DRIVE (0x0030) /* ADOUT Status Select bit */
#define MCF5249_ADC_ADCONFIG_ADCLK (0x000f) /* ADCLK Select bit */
/***********************************************************************/
/* Here we put the modules 1 together. */
/***********************************************************************/
typedef volatile union
{
MCF5249_GPIO gpio;
MCF5249_SINT sint;
MCF5249_PLL pll;
MCF5249_IDE ide;
MCF5249_IIC2 iic2;
MCF5249_IIS iis;
MCF5249_ADC adc;
} MCF5249_IMM2;
#endif // _CPU_MCF5249_H
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -