📄 mcf5249.h
字号:
uint8 DIVR3; /* DMA 3 Interrupt Vector Register */
} MCF5249_DMA;
#define MCF5249_DMA_DCR_INT (0x8000) /* Interrupt on Completion */
#define MCF5249_DMA_DCR_EEXT (0x4000) /* Enable External Request */
#define MCF5249_DMA_DCR_CS (0x2000) /* Cycle Steal */
#define MCF5249_DMA_DCR_AA (0x1000) /* Auto Align */
#define MCF5249_DMA_DCR_BWC_DMA (0x0000) /* Bandwidth: DMA Priority */
#define MCF5249_DMA_DCR_BWC_512 (0x0200) /* Bandwidth: 512 Bytes */
#define MCF5249_DMA_DCR_BWC_1024 (0x0400) /* Bandwidth: 1024 Bytes */
#define MCF5249_DMA_DCR_BWC_2048 (0x0600) /* Bandwidth: 2048 Bytes */
#define MCF5249_DMA_DCR_BWC_4096 (0x0800) /* Bandwidth: 4096 Bytes */
#define MCF5249_DMA_DCR_BWC_8192 (0x0a00) /* Bandwidth: 8192 Bytes */
#define MCF5249_DMA_DCR_BWC_16384 (0x0c00) /* Bandwidth: 16384 Bytes */
#define MCF5249_DMA_DCR_BWC_32768 (0x0e00) /* Bandwidth: 32768 Bytes */
#define MCF5249_DMA_DCR_SAA (0x0100) /* Single Address Access */
#define MCF5249_DMA_DCR_SRW (0x0080) /* Forces MRW Signal High */
#define MCF5249_DMA_DCR_SINC (0x0040) /* Source Increment */
#define MCF5249_DMA_DCR_SSIZE_LONG (0x0000) /* Source Size: Longword */
#define MCF5249_DMA_DCR_SSIZE_BYTE (0x0010) /* Source Size: Byte */
#define MCF5249_DMA_DCR_SSIZE_WORD (0x0020) /* Source Size: uint16 */
#define MCF5249_DMA_DCR_SSIZE_LINE (0x0030) /* Source Size: Line */
#define MCF5249_DMA_DCR_DINC (0x0008) /* Destination Increment */
#define MCF5249_DMA_DCR_DSIZE_LONG (0x0000) /* Destination Size: Longword */
#define MCF5249_DMA_DCR_DSIZE_BYTE (0x0002) /* Destination Size: Byte */
#define MCF5249_DMA_DCR_DSIZE_WORD (0x0004) /* Destination Size: uint16 */
#define MCF5249_DMA_DCR_START (0x0001) /* Start Transfer */
#define MCF5249_DMA_DSR_CE (0x40) /* Configuration Error */
#define MCF5249_DMA_DSR_BES (0x20) /* Bus Error on Source */
#define MCF5249_DMA_DSR_BED (0x10) /* Bus Error on Destination */
#define MCF5249_DMA_DSR_REQ (0x04) /* Request */
#define MCF5249_DMA_DSR_BSY (0x02) /* Busy */
#define MCF5249_DMA_DSR_DONE (0x01) /* Transaction Done */
/***********************************************************************/
/* QSPI Registers */
/***********************************************************************/
typedef volatile struct
{
uint8 reserved0[0x400];
uint16 QMR; /* QSPI Mode Register */
uint16 reserved1;
uint16 QDLYR; /* QSPI Delay Register */
uint16 reserved2;
uint16 QWR; /* QSPI Wrap Register */
uint16 reserved3;
uint16 QIR; /* QSPI Interrupt Register */
uint16 reserved4;
uint16 QAR; /* QSPI Address Register */
uint16 reserved5;
uint16 QDR; /* QSPI Data Register */
} MCF5249_QSPI;
#define MCF5249_QSPI_QMR_MSTR (0x8000) /* Master Mode Enable */
#define MCF5249_QSPI_QMR_DOHIE (0x4000) /* Data Output High Impedance Enable */
#define MCF5249_QSPI_QMR_BITS (0x3C00) /* Transfer Size */
#define MCF5249_QSPI_QMR_CPOL (0x0200) /* Clock Polarity */
#define MCF5249_QSPI_QMR_CPHA (0x0100) /* Clock Phase */
#define MCF5249_QSPI_QMR_BAUD (0x00FF) /* Baud Rate Divider */
#define MCF5249_QSPI_QDLYR_SPE (0x8000) /* QSPI Enable */
#define MCF5249_QSPI_QDLYR_QCD (0x7F00) /* QSPI Clock Delay */
#define MCF5249_QSPI_QDLYR_DTL (0x00FF) /* Delay After Transfer */
#define MCF5249_QSPI_QWR_HALT (0x8000) /* Halt Transfers */
#define MCF5249_QSPI_QWR_WREN (0x4000) /* Wraparound Enable */
#define MCF5249_QSPI_QWR_WRTO (0x2000) /* Wraparound Location */
#define MCF5249_QSPI_QWR_CSIV (0x1000) /* QSPI Chip Select Inactive Level */
#define MCF5249_QSPI_QWR_ENDQP (0x0F00) /* End of Queue Pointer */
#define MCF5249_QSPI_QWR_CPTQP (0x00F0) /* Completed Queue Entry Pointer */
#define MCF5249_QSPI_QWR_NEWQP (0x000F) /* Start of Queue Pointer */
#define MCF5249_QSPI_QIR_WCEFB (0x8000) /* Write Collision Access Error Enable */
#define MCF5249_QSPI_QIR_ABRTB (0x4000) /* Abort Access Error Enable */
#define MCF5249_QSPI_QIR_ABRTL (0x1000) /* Abort Lock Out */
#define MCF5249_QSPI_QIR_WCEFE (0x0800) /* Write Collision Interrupt Enable */
#define MCF5249_QSPI_QIR_ABRTE (0x0400) /* Abort Interrupt Enable */
#define MCF5249_QSPI_QIR_SPIFE (0x0100) /* QSPI Finished Interrupt Enable */
#define MCF5249_QSPI_QIR_WCEF (0x0008) /* Write Collision Error Flag */
#define MCF5249_QSPI_QIR_ABRT (0x0004) /* Abort Flag */
#define MCF5249_QSPI_QIR_SPIF (0x0001) /* QSPI Finished Flag */
/***********************************************************************/
/* Here we put the modules 0 together. */
/***********************************************************************/
typedef volatile union
{
MCF5249_SIM sim;
MCF5249_CS cs;
MCF5249_DRAMC dramc;
MCF5249_TIMER timer;
MCF5249_UART1 uart1;
MCF5249_UART2 uart2;
MCF5249_MBUS mbus;
MCF5249_DMA dma;
MCF5249_QSPI qspi;
} MCF5249_IMM;
/***********************************************************************/
/***********************************************************************/
/***********************************************************************/
/***********************************************************************/
/***********************************************************************/
/***********************************************************************/
/* GPIO Registers */
/***********************************************************************/
typedef volatile struct
{
uint32 GRR; /* GPIO Input Value Register */ /* 0-31 */
uint32 GOR; /* GPIO Output Value Register */
uint32 GER; /* GPIO Output Enable Register */
uint32 GFR; /* GPIO Funtion Select Register */
uint32 reserved1[0x28];
uint32 G1RR; /* GPIO1 Input Value Register */ /* 32-63 */
uint32 G1OR; /* GPIO1 Output Value Register */
uint32 G1ER; /* GPIO1 Output Enable Register */
uint32 G1FR; /* GPIO1 Funtion Select Register */
uint32 GIS; /* GPIO Interrupt status Register */
uint32 GIEN; /* GPIO Interrupt Enable Register */
} MCF5249_GPIO;
#define MCF5249_GPIO0 (0x00000001) /* GPIO0 */
#define MCF5249_GPIO32 (0x00000001) /* GPIO32 */
#define MCF5249_GPIO1 (0x00000002) /* GPIO1 */
#define MCF5249_GPIO33 (0x00000002) /* GPIO32 */
#define MCF5249_GPIO2 (0x00000004) /* GPIO2 */
#define MCF5249_GPIO34 (0x00000004) /* GPIO32 */
#define MCF5249_GPIO3 (0x00000008) /* GPIO3 */
#define MCF5249_GPIO35 (0x00000008) /* GPIO32 */
#define MCF5249_GPIO4 (0x00000010) /* GPIO4 */
#define MCF5249_GPIO36 (0x00000010) /* GPIO32 */
#define MCF5249_GPIO5 (0x00000020) /* GPIO5 */
#define MCF5249_GPIO37 (0x00000020) /* GPIO32 */
#define MCF5249_GPIO6 (0x00000040) /* GPIO6 */
#define MCF5249_GPIO38 (0x00000040) /* GPIO32 */
#define MCF5249_GPIO7 (0x00000080) /* GPIO7 */
#define MCF5249_GPIO39 (0x00000080) /* GPIO32 */
#define MCF5249_GPIO8 (0x00000100) /* GPIO8 */
#define MCF5249_GPIO40 (0x00000100) /* GPIO32 */
#define MCF5249_GPIO9 (0x00000200) /* GPIO9 */
#define MCF5249_GPIO41 (0x00000200) /* GPIO32 */
#define MCF5249_GPIO10 (0x00000400) /* GPIO10 */
#define MCF5249_GPIO42 (0x00000400) /* GPIO32 */
#define MCF5249_GPIO11 (0x00000800) /* GPIO11 */
#define MCF5249_GPIO43 (0x00000800) /* GPIO32 */
#define MCF5249_GPIO12 (0x00001000) /* GPIO12 */
#define MCF5249_GPIO44 (0x00001000) /* GPIO32 */
#define MCF5249_GPIO13 (0x00002000) /* GPIO13 */
#define MCF5249_GPIO45 (0x00002000) /* GPIO32 */
#define MCF5249_GPIO14 (0x00004000) /* GPIO14 */
#define MCF5249_GPIO46 (0x00004000) /* GPIO32 */
#define MCF5249_GPIO15 (0x00008000) /* GPIO15 */
//#define MCF5249_GPIO47 (0x00008000) /* GPIO32 */
#define MCF5249_GPIO16 (0x00010000) /* GPIO0 */
#define MCF5249_GPIO48 (0x00010000) /* GPIO32 */
#define MCF5249_GPIO17 (0x00020000) /* GPIO0 */
#define MCF5249_GPIO49 (0x00020000) /* GPIO32 */
#define MCF5249_GPIO18 (0x00040000) /* GPIO0 */
#define MCF5249_GPIO50 (0x00040000) /* GPIO32 */
#define MCF5249_GPIO19 (0x00080000) /* GPIO0 */
#define MCF5249_GPIO51 (0x00080000) /* GPIO32 */
#define MCF5249_GPIO20 (0x00100000) /* GPIO0 */
#define MCF5249_GPIO52 (0x00100000) /* GPIO32 */
#define MCF5249_GPIO21 (0x00200000) /* GPIO0 */
#define MCF5249_GPIO53 (0x00200000) /* GPIO32 */
#define MCF5249_GPIO22 (0x00400000) /* GPIO0 */
#define MCF5249_GPIO54 (0x00400000) /* GPIO32 */
#define MCF5249_GPIO23 (0x00800000) /* GPIO0 */
#define MCF5249_GPIO55 (0x00800000) /* GPIO32 */
#define MCF5249_GPIO24 (0x01000000) /* GPIO0 */
#define MCF5249_GPIO56 (0x01000000) /* GPIO32 */
#define MCF5249_GPIO25 (0x02000000) /* GPIO0 */
#define MCF5249_GPIO57 (0x02000000) /* GPIO32 */
#define MCF5249_GPIO26 (0x04000000) /* GPIO0 */
#define MCF5249_GPIO58 (0x04000000) /* GPIO32 */
#define MCF5249_GPIO27 (0x08000000) /* GPIO0 */
#define MCF5249_GPIO59 (0x08000000) /* GPIO32 */
#define MCF5249_GPIO28 (0x10000000) /* GPIO0 */
#define MCF5249_GPIO60 (0x10000000) /* GPIO32 */
#define MCF5249_GPIO29 (0x20000000) /* GPIO0 */
#define MCF5249_GPIO61 (0x20000000) /* GPIO32 */
#define MCF5249_GPIO30 (0x40000000) /* GPIO0 */
#define MCF5249_GPIO62 (0x40000000) /* GPIO32 */
#define MCF5249_GPIO31 (0x80000000) /* GPIO0 */
#define MCF5249_GPIO63 (0x80000000) /* GPIO32 */
#define MCF5249_GPIO0_LH (0x00000001) /* GPIO0 L-H */
#define MCF5249_GPIO1_LH (0x00000002) /* GPIO1 L-H */
#define MCF5249_GPIO2_LH (0x00000004) /* GPIO2 L-H */
#define MCF5249_GPIO3_LH (0x00000008) /* GPIO3 L-H */
#define MCF5249_GPIO4_LH (0x00000010) /* GPIO4 L-H */
#define MCF5249_GPIO5_LH (0x00000020) /* GPIO5 L-H */
#define MCF5249_GPIO6_LH (0x00000040) /* GPIO6 L-H */
#define MCF5249_GPIO7_LH (0x00000080) /* GPIO7 L-H */
#define MCF5249_GPIO0_HL (0x00000100) /* GPIO0 H-L */
#define MCF5249_GPIO1_HL (0x00000200) /* GPIO1 H-L */
#define MCF5249_GPIO2_HL (0x00000400) /* GPIO2 H-L */
#define MCF5249_GPIO3_HL (0x00000800) /* GPIO3 H-L */
#define MCF5249_GPIO4_HL (0x00001000) /* GPIO4 H-L */
#define MCF5249_GPIO5_HL (0x00002000) /* GPIO5 H-L */
#define MCF5249_GPIO6_HL (0x00004000) /* GPIO6 H-L */
#define MCF5249_GPIO7_HL (0x00008000) /* GPIO7 H-L */
#define MCF5249_CDROM_DN (0x00010000) /* CDROM Decoder Newblock */
/***********************************************************************/
/* Secondary Interrupt Registers */
/***********************************************************************/
typedef volatile struct
{
uint8 reserved0[0x140];
uint32 INTPRI1; /* Secondary Interrupt 0-7 Priority Register */
uint32 INTPRI2; /* Secondary Interrupt 8-15 Priority Register */
uint32 INTPRI3; /* Secondary Interrupt 16-23 Priority Register */
uint32 INTPRI4; /* Secondary Interrupt 24-31 Priority Register */
uint32 INTPRI5; /* Secondary Interrupt 32-39 Priority Register */
uint32 INTPRI6; /* Secondary Interrupt 40-47 Priority Register */
uint32 INTPRI7; /* Secondary Interrupt 48-55 Priority Register */
uint32 INTPRI8; /* Secondary Interrupt 56-63 Priority Register */
uint8 reserved1[0x7];
uint8 SPURVEC; /* Spurious Interrupt Vector Number Register */
uint8 reserved2[0x3];
uint8 INTBASE; /* Interrupt Base Vector Number Register */
} MCF5249_SINT;
#define MCF5249_SINT_INTPRI1_INT0 (0x0000000F) /* Interrupt 0 Level */
#define MCF5249_SINT_INTPRI1_INT1 (0x000000F0) /* Interrupt 1 Level */
#define MCF5249_SINT_INTPRI1_INT2 (0x00000F00) /* Interrupt 2 Level */
#define MCF5249_SINT_INTPRI1_INT3 (0x0000F000) /* Interrupt 3 Level */
#define MCF5249_SINT_INTPRI1_INT4 (0x000F0000) /* Interrupt 4 Level */
#define MCF5249_SINT_INTPRI1_INT5 (0x00F00000) /* Interrupt 5 Level */
#define MCF5249_SINT_INTPRI1_INT6 (0x0F000000) /* Interrupt 6 Level */
#define MCF5249_SINT_INTPRI1_INT7 (0xF0000000) /* Interrupt 7 Level */
#define MCF5249_SINT_INTPRI2_INT8 (0x0000000F) /* Interrupt 8 Level */
#define MCF5249_SINT_INTPRI2_INT9 (0x000000F0) /* Interrupt 9 Level */
#define MCF5249_SINT_INTPRI2_INT10 (0x00000F00) /* Interrupt 10 Level */
#define MCF5249_SINT_INTPRI2_INT11 (0x0000F000) /* Interrupt 11 Level */
#define MCF5249_SINT_INTPRI2_INT12 (0x000F0000) /* Interrupt 12 Level */
#define MCF5249_SINT_INTPRI2_INT13 (0x00F00000) /* Interrupt 13 Level */
#define MCF5249_SINT_INTPRI2_INT14 (0x0F000000) /* Interrupt 14 Level */
#define MCF5249_SINT_INTPRI2_INT15 (0xF0000000) /* Interrupt 15 Level */
#define MCF5249_SINT_INTPRI3_INT16 (0x0000000F) /* Interrupt 16 Level */
#define MCF5249_SINT_INTPRI3_INT17 (0x000000F0) /* Interrupt 17 Level */
#define MCF5249_SINT_INTPRI3_INT18 (0x00000F00) /* Interrupt 18 Level */
#define MCF5249_SINT_INTPRI3_INT19 (0x0000F000) /* Interrupt 19 Level */
#define MCF5249_SINT_INTPRI3_INT20 (0x000F0000) /* Interrupt 20 Level */
#define MCF5249_SINT_INTPRI3_INT21 (0x00F00000) /* Interrupt 21 Level */
#define MCF5249_SINT_INTPRI3_INT22 (0x0F000000) /* Interrupt 22 Level */
#define MCF5249_SINT_INTPRI3_INT23 (0xF0000000) /* Interrupt 23 Level */
#define MCF5249_SINT_INTPRI4_INT24 (0x0000000F) /* Interrupt 24 Level */
#define MCF5249_SINT_INTPRI4_INT25 (0x000000F0) /* Interrupt 25 Level */
#define MCF5249_SINT_INTPRI4_INT26 (0x00000F00) /* Interrupt 26 Level */
#define MCF5249_SINT_INTPRI4_INT27 (0x0000F000) /* Interrupt 27 Level */
#define MCF5249_SINT_INTPRI4_INT28 (0x000F0000) /* Interrupt 28 Level */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -