📄 mcf5249.h
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uint8 reserved25;
uint8 reserved26;
uint8 UIP;
uint8 reserved27;
uint8 reserved28;
uint8 reserved29;
uint8 UOP1;
uint8 reserved30;
uint8 reserved31;
uint8 reserved32;
uint8 UOP0;
} MCF5249_UART1;
typedef volatile struct
{
uint8 reserved1[0x200];
uint8 UMR;
uint8 reserved2;
uint8 reserved3;
uint8 reserved4;
uint8 USR;
uint8 reserved5;
uint8 reserved6;
uint8 reserved7;
uint8 UCR;
uint8 reserved8;
uint8 reserved9;
uint8 reserved10;
uint8 UBUF;
uint8 reserved11;
uint8 reserved12;
uint8 reserved13;
uint8 UACR;
uint8 reserved14;
uint8 reserved15;
uint8 reserved16;
uint8 UIR;
uint8 reserved17;
uint8 reserved18;
uint8 reserved19;
uint8 UBG1;
uint8 reserved20;
uint8 reserved21;
uint8 reserved22;
uint8 UBG2;
uint32 reserved23[4];
uint8 UIVR;
uint8 reserved24;
uint8 reserved25;
uint8 reserved26;
uint8 UIP;
uint8 reserved27;
uint8 reserved28;
uint8 reserved29;
uint8 UOP1;
uint8 reserved30;
uint8 reserved31;
uint8 reserved32;
uint8 UOP0;
} MCF5249_UART2;
#define MCF5249_UART_UMR1_RXRTS (0x80)
#define MCF5249_UART_UMR1_RXIRQ (0x40)
#define MCF5249_UART_UMR1_ERR (0x20)
#define MCF5249_UART_UMR1_PM1 (0x10)
#define MCF5249_UART_UMR1_PM0 (0x08)
#define MCF5249_UART_UMR1_PMT (0x04)
#define MCF5249_UART_UMR1_BC1 (0x02)
#define MCF5249_UART_UMR1_BC0 (0x01)
#define MCF5249_UART_UMR1_PM_MULTI_ADDR (0x1C)
#define MCF5249_UART_UMR1_PM_MULTI_DATA (0x18)
#define MCF5249_UART_UMR1_PM_NONE (0x10)
#define MCF5249_UART_UMR1_PM_FORCE_HI (0x0C)
#define MCF5249_UART_UMR1_PM_FORCE_LO (0x08)
#define MCF5249_UART_UMR1_PM_ODD (0x04)
#define MCF5249_UART_UMR1_PM_EVEN (0x00)
#define MCF5249_UART_UMR1_BC_5 (0x00)
#define MCF5249_UART_UMR1_BC_6 (0x01)
#define MCF5249_UART_UMR1_BC_7 (0x02)
#define MCF5249_UART_UMR1_BC_8 (0x03)
#define MCF5249_UART_UMR2_CM1 (0x80)
#define MCF5249_UART_UMR2_CM0 (0x40)
#define MCF5249_UART_UMR2_TXRTS (0x20)
#define MCF5249_UART_UMR2_TXCTS (0x10)
#define MCF5249_UART_UMR2_SB3 (0x08)
#define MCF5249_UART_UMR2_SB2 (0x04)
#define MCF5249_UART_UMR2_SB1 (0x02)
#define MCF5249_UART_UMR2_SB0 (0x01)
#define MCF5249_UART_UMR2_CM_NORMAL (0x00)
#define MCF5249_UART_UMR2_CM_ECHO (0x40)
#define MCF5249_UART_UMR2_CM_LOCAL_LOOP (0x80)
#define MCF5249_UART_UMR2_CM_REMOTE_LOOP (0xC0)
#define MCF5249_UART_UMR2_STOP_BITS_1 (0x07)
#define MCF5249_UART_UMR2_STOP_BITS_15 (0x08)
#define MCF5249_UART_UMR2_STOP_BITS_2 (0x0F)
#define MCF5249_UART_USR_RB (0x80)
#define MCF5249_UART_USR_FE (0x40)
#define MCF5249_UART_USR_PE (0x20)
#define MCF5249_UART_USR_OE (0x10)
#define MCF5249_UART_USR_TXEMP (0x08)
#define MCF5249_UART_USR_TXRDY (0x04)
#define MCF5249_UART_USR_FFULL (0x02)
#define MCF5249_UART_USR_RXRDY (0x01)
#define MCF5249_UART_UCSR_RCS3 (0x80)
#define MCF5249_UART_UCSR_RCS2 (0x40)
#define MCF5249_UART_UCSR_RCS1 (0x20)
#define MCF5249_UART_UCSR_RCS0 (0x10)
#define MCF5249_UART_UCSR_TCS3 (0x08)
#define MCF5249_UART_UCSR_TCS2 (0x04)
#define MCF5249_UART_UCSR_TCS1 (0x02)
#define MCF5249_UART_UCSR_TCS0 (0x01)
#define MCF5249_UART_UCSR_RX_TIMER (0xD0)
#define MCF5249_UART_UCSR_RX_16EXT (0xE0)
#define MCF5249_UART_UCSR_RX_1EXT (0xF0)
#define MCF5249_UART_UCSR_TX_TIMER (0x0D)
#define MCF5249_UART_UCSR_TX_16EXT (0x0E)
#define MCF5249_UART_UCSR_TX_1EXT (0x0F)
#define MCF5249_UART_UCR_MISC2 (0x40)
#define MCF5249_UART_UCR_MISC1 (0x20)
#define MCF5249_UART_UCR_MISC0 (0x10)
#define MCF5249_UART_UCR_TC1 (0x08)
#define MCF5249_UART_UCR_TC0 (0x04)
#define MCF5249_UART_UCR_RC1 (0x02)
#define MCF5249_UART_UCR_RC0 (0x01)
#define MCF5249_UART_UCR_NONE (0x00)
#define MCF5249_UART_UCR_STOP_BREAK (0x70)
#define MCF5249_UART_UCR_START_BREAK (0x60)
#define MCF5249_UART_UCR_RESET_BKCHGINT (0x50)
#define MCF5249_UART_UCR_RESET_ERROR (0x40)
#define MCF5249_UART_UCR_RESET_TX (0x30)
#define MCF5249_UART_UCR_RESET_RX (0x20)
#define MCF5249_UART_UCR_RESET_MR (0x10)
#define MCF5249_UART_UCR_TX_DISABLED (0x08)
#define MCF5249_UART_UCR_TX_ENABLED (0x04)
#define MCF5249_UART_UCR_RX_DISABLED (0x02)
#define MCF5249_UART_UCR_RX_ENABLED (0x01)
#define MCF5249_UART_UIPCR_COS (0x10)
#define MCF5249_UART_UIPCR_CTS (0x01)
#define MCF5249_UART_UACR_IEC (0x01)
#define MCF5249_UART_UISR_COS (0x80)
#define MCF5249_UART_UISR_DB (0x04)
#define MCF5249_UART_UISR_RXRDY (0x02)
#define MCF5249_UART_UISR_TXRDY (0x01)
#define MCF5249_UART_UIMR_COS (0x80)
#define MCF5249_UART_UIMR_DB (0x04)
#define MCF5249_UART_UIMR_FFULL (0x02)
#define MCF5249_UART_UIMR_TXRDY (0x01)
#define MCF5249_UART_UIP_CTS (0x01)
#define MCF5249_UART_UOP1_RTS (0x01)
#define MCF5249_UART_UOP0_RTS (0x01)
/***********************************************************************/
/* M-BUS Registers */
/***********************************************************************/
typedef volatile struct
{
uint8 reserved0[0x280];
uint8 MADR; /* M-Bus Address Register */
uint8 reserved1;
uint16 reserved2;
uint8 MFDR; /* M-Bus Frequency Divider Register */
uint8 reserved3;
uint16 reserved4;
uint8 MBCR; /* M-Bus Control Register */
uint8 reserved5;
uint16 reserved6;
uint8 MBSR; /* M-Bus Status Register */
uint8 reserved7;
uint16 reserved8;
uint8 MBDR; /* M-Bus Data I/O Register */
} MCF5249_MBUS;
#define MCF5249_MBUS_MADR_ADDR(a) (((a)&0xFE)<<0x01) /* Slave Address */
#define MCF5249_MBUS_MFDR_MBC(a) ((a)&0x3F) /* M-Bus Clock Rate */
#define MCF5249_MBUS_MBCR_MEN (0x80) /* M-Bus Enable */
#define MCF5249_MBUS_MBCR_MIEN (0x40) /* M-Bus Interrupt Enable */
#define MCF5249_MBUS_MBCR_MSTA (0x20) /* Master/Slave Mode Select Bit */
#define MCF5249_MBUS_MBCR_MTX (0x10) /* Transmit/Rcv Mode Select Bit */
#define MCF5249_MBUS_MBCR_TXAK (0x08) /* Transmit Acknowledge Enable */
#define MCF5249_MBUS_MBCR_RSTA (0x04) /* Repeat Start */
#define MCF5249_MBUS_MBSR_MCF (0x80) /* Data Transfer Complete */
#define MCF5249_MBUS_MBSR_MAAS (0x40) /* Addressed as a Slave */
#define MCF5249_MBUS_MBSR_MBB (0x20) /* Bus Busy */
#define MCF5249_MBUS_MBSR_MAL (0x10) /* Arbitration Lost */
#define MCF5249_MBUS_MBSR_SRW (0x04) /* Slave Transmit */
#define MCF5249_MBUS_MBSR_MIF (0x02) /* M-Bus Interrupt */
#define MCF5249_MBUS_MBSR_RXAK (0x01) /* No Acknowledge Received */
/***********************************************************************/
/* DMA Registers */
/***********************************************************************/
typedef volatile struct
{
uint8 reserved0[0x300];
uint32 SAR0; /* DMA 0 Source Address Register */
uint32 DAR0; /* DMA 0 Destination Address Register */
uint16 DCR0; /* DMA 0 Control Register */
uint16 reserved1;
uint16 BCR0; /* DMA 0 Byte Count Register */
uint16 reserved2;
uint8 DSR0; /* DMA 0 Status Register */
uint8 reserved3;
uint16 reserved4;
uint8 DIVR0; /* DMA 0 Interrupt Vector Register */
uint8 reserved5;
uint16 reserved6;
uint32 reserved7[0xa];
uint32 SAR1; /* DMA 1 Source Address Register */
uint32 DAR1; /* DMA 1 Destination Address Register */
uint16 DCR1; /* DMA 1 Control Register */
uint16 reserved8;
uint16 BCR1; /* DMA 1 Byte Count Register */
uint16 reserved9;
uint8 DSR1; /* DMA 1 Status Register */
uint8 reserved10;
uint16 reserved11;
uint8 DIVR1; /* DMA 1 Interrupt Vector Register */
uint8 reserved12;
uint16 reserved13;
uint32 reserved14[0xa];
uint32 SAR2; /* DMA 2 Source Address Register */
uint32 DAR2; /* DMA 2 Destination Address Register */
uint16 DCR2; /* DMA 2 Control Register */
uint16 reserved15;
uint16 BCR2; /* DMA 2 Byte Count Register */
uint16 reserved16;
uint8 DSR2; /* DMA 2 Status Register */
uint8 reserved17;
uint16 reserved18;
uint8 DIVR2; /* DMA 2 Interrupt Vector Register */
uint8 reserved19;
uint16 reserved20;
uint32 reserved21[0xa];
uint32 SAR3; /* DMA 3 Source Address Register */
uint32 DAR3; /* DMA 3 Destination Address Register */
uint16 DCR3; /* DMA 3 Control Register */
uint16 reserved22;
uint16 BCR3; /* DMA 3 Byte Count Register */
uint16 reserved23;
uint8 DSR3; /* DMA 3 Status Register */
uint8 reserved24;
uint16 reserved25;
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