mcf5249.h

用来测试mcf5249的嵌入式测试程序

#define MCF5249_SIM_AVCR_BLK		(0x01)			/* Block Address Strobe */		    

#define MCF5249_SIM_ICR_AVEC		(0x80)			/* Autovector Enable */	    
#define MCF5249_SIM_ICR_IL(a)		(((a)&0x07)<<2)	/* Interrupt Level */	    
#define MCF5249_SIM_ICR_IP_EXT		(0x02)			/* High Priority External */  
#define MCF5249_SIM_ICR_IP_INT		(0x01)			/* High Priority Internal */   

/**********************************************************************/
/*	Chip-Select Module, CS											  */
/**********************************************************************/
typedef volatile struct
{
	uint8	reserved1[0x80];
	uint16	CSAR0;		/* Chip-Select Address Register	- Bank 0 */    
	uint16	reserved2;
	uint32	CSMR0;		/* Chip-Select Mask Register	- Bank 0 */    
	uint16	reserved3;
	uint16	CSCR0;		/* Chip-Select Control Register	- Bank 0 */    
	uint16	CSAR1;		/* Chip-Select Address Register	- Bank 1 */    
	uint16	reserved4;
	uint32	CSMR1;		/* Chip-Select Mask Register	- Bank 1 */    
	uint16	reserved5;
	uint16	CSCR1;		/* Chip-Select Control Register	- Bank 1 */    
	uint16	CSAR2;		/* Chip-Select Address Register	- Bank 2 */    
	uint16	reserved6;
	uint32	CSMR2;		/* Chip-Select Mask Register	- Bank 2 */    
	uint16	reserved7;
	uint16	CSCR2;		/* Chip-Select Control Register	- Bank 2 */    
	uint16	CSAR3;		/* Chip-Select Address Register	- Bank 3 */    
	uint16	reserved8;
	uint32	CSMR3;		/* Chip-Select Mask Register	- Bank 3 */    
	uint16	reserved9;
	uint16	CSCR3;		/* Chip-Select Control Register	- Bank 3 */    
} MCF5249_CS;

/*  These definitions only exists in the CSMR for Banks 0 and 1. */		
#define MCF5249_CS_CSMR_MASK_4G		(0xFFFF0000)	/* Set Bank to 4G */	
#define MCF5249_CS_CSMR_MASK_2G		(0x7FFF0000)	/* Set Bank to 2G */	
#define MCF5249_CS_CSMR_MASK_1G		(0x3FFF0000)	/* Set Bank to 1G */	
#define MCF5249_CS_CSMR_MASK_1024M	(0x3FFF0000)	/* Set Bank to 1024M */
#define MCF5249_CS_CSMR_MASK_512M	(0x1FFF0000)	/* Set Bank to 512M */	
#define MCF5249_CS_CSMR_MASK_256M	(0x0FFF0000)	/* Set Bank to 256M */	
#define MCF5249_CS_CSMR_MASK_128M	(0x07FF0000)	/* Set Bank to 128M */	
#define MCF5249_CS_CSMR_MASK_64M	(0x03FF0000)	/* Set Bank to 64M */	
#define MCF5249_CS_CSMR_MASK_32M	(0x01FF0000)	/* Set Bank to 32M */	
#define MCF5249_CS_CSMR_MASK_16M	(0x00FF0000)	/* Set Bank to 16M */	
#define MCF5249_CS_CSMR_MASK_8M		(0x007F0000)	/* Set Bank to 8M */	
#define MCF5249_CS_CSMR_MASK_4M		(0x003F0000)	/* Set Bank to 4M */	
#define MCF5249_CS_CSMR_MASK_2M		(0x001F0000)	/* Set Bank to 2M */	
#define MCF5249_CS_CSMR_MASK_1M		(0x000F0000)	/* Set Bank to 1M */	
#define MCF5249_CS_CSMR_MASK_1024K	(0x000F0000)	/* Set Bank to 1024K */
#define MCF5249_CS_CSMR_MASK_512K	(0x00070000)	/* Set Bank to 512K	*/
#define MCF5249_CS_CSMR_MASK_256K	(0x00030000)	/* Set Bank to 256K */
#define MCF5249_CS_CSMR_MASK_128K	(0x00010000)	/* Set Bank to 128K */
#define MCF5249_CS_CSMR_MASK_64K	(0x00000000)	/* Set Bank to 64K */	
#define MCF5249_CS_CSMR_CPU			(0x00000020)	/* CPU and IACK Cycle Mask */ 

/*  The following definitions exist for all Banks 0-7 */					
#define MCF5249_CS_CSAR(a)		(((a)&0xFFFF0000)>>16)	/* Base Address */		
#define MCF5249_CS_CSBARx(a)	(((a)&0xFF000000)>>24)	/* Base for CS2-7 */	

#define MCF5249_CS_CSMR_WP		(0x00000100)	/* Write Protect */			
#define MCF5249_CS_CSMR_AM		(0x00000040)	/* Alternate Master Mask */	
#define MCF5249_CS_CSMR_CI		(0x00000020)	/* Interrupt Cycle Mask */		
#define MCF5249_CS_CSMR_SC		(0x00000010)	/* Supervisor Code Mask */		
#define MCF5249_CS_CSMR_SD		(0x00000008)	/* Supervisor Data Mask */		
#define MCF5249_CS_CSMR_UC		(0x00000004)	/* User Code Mask */			
#define MCF5249_CS_CSMR_UD		(0x00000002)	/* User Data Mask */			
#define MCF5249_CS_CSMR_V		(0x00000001)	/* Valid Register */			

#define MCF5249_CS_CSCR_WS(a)	(((a)&0x0F)<<10) /* Wait States */				
#define MCF5249_CS_CSCR_AA		(0x0100)		/* Auto Acknowledge Enable */	
#define MCF5249_CS_CSCR_PS_8	(0x0040)		/* Port Size:   8-bit */		
#define MCF5249_CS_CSCR_PS_16	(0x0080)		/* Port Size:  16-bit */		
#define MCF5249_CS_CSCR_PS_32	(0x0000)		/* Port Size:  32-bit */		
#define MCF5249_CS_CSCR_BEM		(0x0020)		/* Byte Module Enable */		
#define MCF5249_CS_CSCR_BSTR	(0x0010)		/* Burst Read Enable */		
#define MCF5249_CS_CSCR_BSTW	(0x0008)		/* Burst Write Enable */		

/**********************************************************************/
/*	DRAM Controller Module, DRAMC									  */
/**********************************************************************/
typedef volatile struct
{
	uint8	reserved1[0x100];
	uint16	DCR;		/* DRAM Control Register */				
	uint16	reserved2;
	uint32	reserved3;
	uint32	DACR0;		/* DRAM Address and Control Register 0 */	
	uint32	DMR0;		/* DRAM Controller Mask Register 0 */		
	uint32	DACR1;		/* DRAM Address and Control Register 1 */	
	uint32	DMR1;		/* DRAM Controller Mask Register 1 */		
} MCF5249_DRAMC;
 
/* Controls used by both Synchronous and Asynchronous DRAM */			
#define MCF5249_DRAMC_DCR_SO			(0x8000)		/* Synchronous Operation */	
#define MCF5249_DRAMC_DCR_NAM			(0x2000)		/* No Address Multiplexing */	
#define MCF5249_DRAMC_DCR_RC(a)			((a)&0x01FF)	/* Refresh Count */			

#define MCF5249_DRAMC_DACR_BASE(a)		((a)&0xFFFC0000) /* Base Address */			
#define MCF5249_DRAMC_DACR_RE			(0x00008000)	/* Refresh Enable */			
#define MCF5249_DRAMC_DACR_PS_32		(0x00000000)	/* Port Size:  32-bit */		
#define MCF5249_DRAMC_DACR_PS_8			(0x00000010)	/* Port Size:   8-bit */		
#define MCF5249_DRAMC_DACR_PS_16		(0x00000020)	/* Port Size:  16-bit */		

#define MCF5249_DRAMC_DCMR_MASK_4G		(0xFFFC0000)	/* DRAM Size of 4G */			
#define MCF5249_DRAMC_DCMR_MASK_2G		(0x7FFC0000)	/* DRAM Size of 2G */			
#define MCF5249_DRAMC_DCMR_MASK_1G		(0x3FFC0000)	/* DRAM Size of 1G */			
#define MCF5249_DRAMC_DCMR_MASK_1024M	(0x3FFC0000)	/* DRAM Size of 1024M */	
#define MCF5249_DRAMC_DCMR_MASK_512M	(0x1FFC0000)	/* DRAM Size of 512M */	
#define MCF5249_DRAMC_DCMR_MASK_256M	(0x0FFC0000)	/* DRAM Size of 256M */	
#define MCF5249_DRAMC_DCMR_MASK_128M	(0x07FC0000)	/* DRAM Size of 128M */	
#define MCF5249_DRAMC_DCMR_MASK_64M		(0x03FC0000)	/* DRAM Size of 64M */			
#define MCF5249_DRAMC_DCMR_MASK_32M		(0x01FC0000)	/* DRAM Size of 32M */			
#define MCF5249_DRAMC_DCMR_MASK_16M		(0x00FC0000)	/* DRAM Size of 16M	*/		
#define MCF5249_DRAMC_DCMR_MASK_8M		(0x007C0000)	/* DRAM Size of 8M */			
#define MCF5249_DRAMC_DCMR_MASK_4M		(0x003C0000)	/* DRAM Size of 4M */			
#define MCF5249_DRAMC_DCMR_MASK_2M		(0x001C0000)	/* DRAM Size of 2M */			
#define MCF5249_DRAMC_DCMR_MASK_1M		(0x000C0000)	/* DRAM Size of 1M */			
#define MCF5249_DRAMC_DCMR_MASK_1024K	(0x00040000)	/* DRAM Size of 1024K */		
#define MCF5249_DRAMC_DCMR_MASK_512K	(0x00000000)	/* DRAM Size of 512K */		
#define MCF5249_DRAMC_DCMR_WP			(0x00000100)	/* Write Protect */		
#define MCF5249_DRAMC_DCMR_CPU			(0x00000040)	/* CPU Space Ignored */		
#define MCF5249_DRAMC_DCMR_AM			(0x00000020)	/* Alternate Master Ignored */	
#define MCF5249_DRAMC_DCMR_SC			(0x00000010)	/* Supervisor Code Ignored */	
#define MCF5249_DRAMC_DCMR_SD			(0x00000008)	/* Supervisor Data Ignored */	
#define MCF5249_DRAMC_DCMR_UC			(0x00000004)	/* User Code Ignored */		
#define MCF5249_DRAMC_DCMR_UD			(0x00000002)	/* User Data Ignored */		
#define MCF5249_DRAMC_DCMR_V			(0x00000001)	/* Valid Register */		

/* Controls used only by Asynchronous DRAM*/				
#define MCF5249_DRAMC_DCR_RRA_2			(0x0000)		/* Refresh RAS Asserted 2 Clocks */	
#define MCF5249_DRAMC_DCR_RRA_3			(0x0800)		/* Refresh RAS Asserted 3 Clocks */	
#define MCF5249_DRAMC_DCR_RRA_4			(0x1000)		/* Refresh RAS Asserted 4 Clocks */	
#define MCF5249_DRAMC_DCR_RRA_5			(0x1800)		/* Refresh RAS Asserted 5 Clocks */	
#define MCF5249_DRAMC_DCR_RRP_1			(0x0000)		/* Refresh RAS Precharged 3 Clks */	
#define MCF5249_DRAMC_DCR_RRP_2			(0x0200)		/* Refresh RAS Precharged 3 Clks */	
#define MCF5249_DRAMC_DCR_RRP_3			(0x0400)		/* Refresh RAS Precharged 3 Clks */	
#define MCF5249_DRAMC_DCR_RRP_4			(0x0600)		/* Refresh RAS Precharged 3 Clks */	

#define MCF5249_DRAMC_DACR_CAS_1		(0x00000000)	/* CAS Active 1 Clock */	 	
#define MCF5249_DRAMC_DACR_CAS_2		(0x00001000)	/* CAS Active 2 Clocks */	 	
#define MCF5249_DRAMC_DACR_CAS_3		(0x00002000)	/* CAS Active 3 Clocks */	 	
#define MCF5249_DRAMC_DACR_CAS_4		(0x00003000)	/* CAS Active 4 Clocks */	 	
#define MCF5249_DRAMC_DACR_RP_1			(0x00000000)	/* RAS Precharge 1 Clock */ 	
#define MCF5249_DRAMC_DACR_RP_2			(0x00000400)	/* RAS Precharge 2 Clocks */	
#define MCF5249_DRAMC_DACR_RP_3			(0x00000800)	/* RAS Precharge 3 Clocks */
#define MCF5249_DRAMC_DACR_RP_4			(0x00000C00)	/* RAS Precharge 4 Clocks */	
#define MCF5249_DRAMC_DACR_RNCN			(0x00000200)	/* RAS Negate to CAS Negate	 */
#define MCF5249_DRAMC_DACR_RCD_1		(0x00000000)	/* 1 Clock Between RAS and CAS */	
#define MCF5249_DRAMC_DACR_RCD_2		(0x00000100)	/* 2 Clocks Between RAS and CAS */
#define MCF5249_DRAMC_DACR_EDO			(0x00000040)	/* Extended Data Out */
#define MCF5249_DRAMC_DACR_PM_OFF		(0x00000000)	/* No Page Mode */	
#define MCF5249_DRAMC_DACR_PM_BURST		(0x00000004)	/* Page Mode on Burst Only */
#define MCF5249_DRAMC_DACR_PM_ON		(0x0000000C)	/* Continuous Page Mode */

/*	Controls used only by Synchronous DRAM */
#define MCF5249_DRAMC_DCR_COC		(0x1000) /* Command on Clock Enable */
#define MCF5249_DRAMC_DCR_IS		(0x0800) /* Initiate Self Refresh Command */
#define MCF5249_DRAMC_DCR_RTIM_3	(0x0000) /* 3 Clocks Between REF and ACTV Cmds */
#define MCF5249_DRAMC_DCR_RTIM_6	(0x0200) /* 6 Clocks Between REF and ACTV Cmds */
#define MCF5249_DRAMC_DCR_RTIM_9	(0x0400) /* 9 Clocks Between REF and ACTV Cmds */

#define MCF5249_DRAMC_DACR_CASL_1	(0x00000000) /* 1 Clock From CAS to Data */
#define MCF5249_DRAMC_DACR_CASL_2	(0x00001000) /* 2 Clock From CAS to Data */	
#define MCF5249_DRAMC_DACR_CASL_3	(0x00002000) /* 3 Clock From CAS to Data */	
#define MCF5249_DRAMC_DACR_CBM(a)	(((a)&0x00000007)<<8) /* Command and Bank Mux */
#define MCF5249_DRAMC_DACR_IMRS		(0x00000040) /* Initiate Mode Register Set Cmd */
#define MCF5249_DRAMC_DACR_IP		(0x00000008) /* Initiate Precharge All Command */
#define MCF5249_DRAMC_DACR_PM		(0x00000004) /* Continuous Page	Mode */

/***********************************************************************/
/*  Timer Registers													   */
/***********************************************************************/
typedef volatile struct
{
	uint8	reserved0[0x140];
	uint16	TMR0;		/* Timer 1 Mode Register */	
	uint16	reserved1;
	uint16	TRR0;		/* Timer 1 Reference Register */	
	uint16	reserved2;
	uint16	TCR0;		/* Timer 1 Capture Register */	
	uint16	reserved3;
	uint16	TCN0;		/* Timer 1 Counter */		
	uint16	reserved4;
	uint8	reserved5;
	uint8	TER0;		/* Timer 1 Event Register */	
	uint16	reserved6;
	uint32	reserved7[11];
	uint16	TMR1;		/* Timer 2 Mode Register */	
	uint16	reserved8;
	uint16	TRR1;		/* Timer 2 Reference Register */	
	uint16	reserved9;
	uint16	TCR1;		/* Timer 2 Capture Register */	
	uint16	reserved10;
	uint16	TCN1;		/* Timer 2 Counter */		
	uint16	reserved11;
	uint8	reserved12;
	uint8	TER1;		/* Timer 2 Event Register */	
} MCF5249_TIMER;

#define MCF5249_TIMER_TMR_PS(a)		(((a)&0x00FF)<<8) /* Prescaler Value */		
#define MCF5249_TIMER_TMR_CE_ANY	(0x00C0) /* Capture on Any Edge */			
#define MCF5249_TIMER_TMR_CE_FALL	(0x0080) /* Capture on Falling Edge */		
#define MCF5249_TIMER_TMR_CE_RISE	(0x0040) /* Capture on Rising Edge */		
#define MCF5249_TIMER_TMR_CE_NONE	(0x0000) /* Disable Capture Event */		
#define MCF5249_TIMER_TMR_OM		(0x0020) /* Output Mode */				
#define MCF5249_TIMER_TMR_ORI		(0x0010) /* Output Reference Interrupt Enable */	
#define MCF5249_TIMER_TMR_FRR		(0x0008) /* Restart After Reference Value */	
#define MCF5249_TIMER_TMR_CLK_TIN	(0x0006) /* TIN is Input Clock Source */		
#define MCF5249_TIMER_TMR_CLK_DIV16	(0x0004) /* Sys Clk / 16 is Input Clock Source */	
#define MCF5249_TIMER_TMR_CLK_MSCLK	(0x0002) /* Sys Clk is Input Clock Source */	
#define MCF5249_TIMER_TMR_CLK_STOP	(0x0000) /* Stop Count */				
#define MCF5249_TIMER_TMR_RST		(0x0001) /* Enable Timer */			

#define MCF5249_TIMER_TER_REF		(0x02)	/* Output Reference Event */		
#define MCF5249_TIMER_TER_CAP		(0x01)	/* Capture Event */			

/**********************************************************************/
/*	UART Module, UART												  */
/**********************************************************************/
typedef volatile struct
{
	uint8	reserved1[0x1C0];
	uint8	UMR;
	uint8	reserved2;
	uint8	reserved3;
	uint8	reserved4;
	uint8	USR;
	uint8	reserved5;
	uint8	reserved6;
	uint8	reserved7;
	uint8	UCR;
	uint8	reserved8;
	uint8	reserved9;
	uint8	reserved10;
	uint8	UBUF;
	uint8	reserved11;
	uint8	reserved12;
	uint8	reserved13;
	uint8	UACR;
	uint8	reserved14;
	uint8	reserved15;
	uint8	reserved16;
	uint8	UIR;
	uint8	reserved17;
	uint8	reserved18;
	uint8	reserved19;
	uint8	UBG1;
	uint8	reserved20;
	uint8	reserved21;
	uint8	reserved22;
	uint8	UBG2;
	uint32	reserved23[4];
	uint8	UIVR;
	uint8	reserved24;