mcf5249.h

用来测试mcf5249的嵌入式测试程序

/*
 * File:		cpu/MCF5200/MCF5249.h
 * Purpose:		MCF5249 definitions
 *
 * Notes:		This file automatically included.
 *
 * Author:		Michael Norman
 * Date:		3-11-99
 * 
 * Modifications:
 *		
 *		User: Li KunHua		Date:4/19/2000 
 *
 */

#ifndef _CPU_MCF5249_H
#define _CPU_MCF5249_H

#include "type.h"

/***********************************************************************/
/***********************************************************************/
/***********************************************************************/

/* Turn off C++ so functions can call assembly routines */
//#pragma cplusplus off
//#pragma 6aframes off

/***********************************************************************/
/*
 * Common M68K & ColdFire definitions
 */
//#define ADDRESS			uint32
//#define INSTRUCTION		uint16
//#define ILLEGAL			0x4AFC
//#define CPU_WORD_SIZE	16

/***********************************************************************/
/*
 * Routines and macros for accessing Input/Output devices
 */
#define cpu_iord_8(ADDR)        *((volatile uint8 *)(ADDR))
#define cpu_iord_16(ADDR)       *((volatile uint16 *)(ADDR))
#define cpu_iord_32(ADDR)       *((volatile uint32 *)(ADDR))

#define cpu_iowr_8(ADDR,DATA)   *((volatile uint8 *)(ADDR)) = (DATA)
#define cpu_iowr_16(ADDR,DATA)  *((volatile uint16 *)(ADDR)) = (DATA)
#define cpu_iowr_32(ADDR,DATA)  *((volatile uint32 *)(ADDR)) = (DATA)

/***********************************************************************/
/*
 * The ColdFire family of processors has a simplified exception stack
 * frame that looks like the following:
 *
 *              3322222222221111 111111
 *              1098765432109876 5432109876543210
 *           8 +----------------+----------------+
 *             |         Program Counter         |
 *           4 +----------------+----------------+
 *             |FS/Fmt/Vector/FS|      SR        |
 *   SP -->  0 +----------------+----------------+
 *
 * The stack self-aligns to a 4-byte boundary at an exception, with
 * the FS/Fmt/Vector/FS field indicating the size of the adjustment
 * (SP += 0,1,2,3 bytes).
 */
#define MCF5200_SR_T		(0x8000)
#define MCF5200_SR_S		(0x2000)
#define MCF5200_SR_M		(0x1000)
#define MCF5200_SR_IPL		(0x0700)
#define MCF5200_SR_IPL_0	(0x0000)
#define MCF5200_SR_IPL_1	(0x0100)
#define MCF5200_SR_IPL_2	(0x0200)
#define MCF5200_SR_IPL_3	(0x0300)
#define MCF5200_SR_IPL_4	(0x0400)
#define MCF5200_SR_IPL_5	(0x0500)
#define MCF5200_SR_IPL_6	(0x0600)
#define MCF5200_SR_IPL_7	(0x0700)
#define MCF5200_SR_X		(0x0010)
#define MCF5200_SR_N		(0x0008)
#define MCF5200_SR_Z		(0x0004)
#define MCF5200_SR_V		(0x0002)
#define MCF5200_SR_C		(0x0001)

/**********************************************************************/
/*	Cache and Access Control Register routines and defintions         */
/**********************************************************************/
#define MCF5249_CACR_EC		(0x80000000)		/* Cache Enable */
#define MCF5249_CACR_ESB	(0x20000000)		/* Enable Store Buffer */		    
#define MCF5249_CACR_DPI	(0x10000000)		/* Disable CPUSHL Invalidation */ 	
#define MCF5249_CACR_HLCK	(0x08000000)		/* 1/2 Cache Lock Mode */		    
#define MCF5249_CACR_CINVA	(0x01000000)		/* Cache Invalidate All */ 	    
#define MCF5249_CACR_DNFB	(0x00000400)		/* Default Noncacheable Fill Buffer */ 
#define MCF5249_CACR_DCM_00	(0x00000000)		/* Cacheable, writethrough */	    
#define MCF5249_CACR_DCM_01	(0x00000100)		/* Cacheable, copyback */		    
#define MCF5249_CACR_DCM_10	(0x00000200)		/* Cache-Inhibited, precise */    
#define MCF5249_CACR_DCM_11	(0x00000300)		/* Cache-Inhibited, imprecise */   
#define MCF5249_CACR_DW		(0x00000020)		/* Default Write Protect */	    

#define MCF5249_ACR_BASE(a)	((a)&0xFF000000)	/* Address Base */				
#define MCF5249_ACR_MASK(a)	(((a)&0xFF000000)>>8)	/* Address Mask */		    
#define MCF5249_ACR_E		(0x00008000)		/* Enable */						
#define MCF5249_ACR_S_USER	(0x00000000)		/* User Mode Access */				
#define MCF5249_ACR_S_SUPER	(0x00002000)		/* Supervisor Mode Access */	    
#define MCF5249_ACR_S_IGNORE	(0x00004000)	/* Ignore Mode Access */	    
#define MCF5249_ACR_CM_00	(0x00000000)		/* Cacheable, writethrough */	    
#define MCF5249_ACR_CM_01	(0x00000020)		/* Cacheable, copyback */		    
#define MCF5249_ACR_CM_10	(0x00000040)		/* Cache-Inhibited, precise */	    
#define MCF5249_ACR_CM_11	(0x00000060)		/* Cache-Inhibited, imprecise */	
#define MCF5249_ACR_WP		(0x00000004)		/* Write Protect */				

#define MCF5249_VBR_BASE(a)	((a)&0xFFF00000)	/* Vector Base Address */	    

#define MCF5249_RAMBAR_BASE(a)	((a)&0xFFFFFE00)	/* Base Address */		    
#define MCF5249_RAMBAR_WP	(0x00000100)		/* Write Protect */		    
#define MCF5249_RAMBAR_AS_CPU	(0x00000020)	/* CPU Space/Interrupt acknowledge */  
#define MCF5249_RAMBAR_AS_SC	(0x00000010)	/* Supervisor Code */		    
#define MCF5249_RAMBAR_AS_SD	(0x00000008)	/* Supervisor Data */		    
#define MCF5249_RAMBAR_AS_UC	(0x00000004)	/* User Code */			    
#define MCF5249_RAMBAR_AS_UD	(0x00000002)	/* User Data */			    
#define MCF5249_RAMBAR_V	(0x00000001)		/* Valid */ 					

#define MCF5249_MBAR_BASE(a)	((a)&0xFFFFFC00)	/* Base Address */		    
#define MCF5249_MBAR_WP		(0x00000200)		/* Write Protect */				
#define MCF5249_MBAR_SC		(0x00000010)		/* Mask Supervisor Code Space */	
#define MCF5249_MBAR_SD		(0x00000008)		/* Mask Supervisor Data Space */	
#define MCF5249_MBAR_UC		(0x00000004)		/* Mask User Code Space */		    
#define MCF5249_MBAR_UD		(0x00000002)		/* Mask User Data Space	*/	    
#define MCF5249_MBAR_V		(0x00000001)		/* Valid */						

/**********************************************************************/
/*	System Integration Modules, SIM									  */
/**********************************************************************/
typedef volatile struct
{
	uint8	RSR;		/* Reset Status Register */		    
	uint8	SYPCR;		/* System Protection Control Register */	    
	uint8	SWIVR;		/* Software Watchdog Interrupt Vector Reg */   
	uint8	SWSR;		/* Software Watchdog Service Register */	    
	uint16	reserved0;  /* No longer exists on 5249	 Pin Assignment Register */		    
	uint16	reserved1;  /*IRQPAR;		/* Interrupt Assignment Register */	    
	uint16	reserved2;  /*on 5349 this reg is off MBAR2	/* Phase Locked Loop Control Register */	    
	uint16	reserved3;
	uint8	MARBCR;		/* MBus Park Register */			    
	uint8	reserved4[3];
	uint32	reserved5[12];
	uint32	IPR;		/* Interrupt Pending Register */		    
	uint32	IMR;		/* Internal Mask Register */		    
	uint8	reserved6[3];
	uint8	AVCR;		/* Auto Vector Control Register */		    
	uint8	ICR0;		/* Interrupt Control Register:  SWT */	    
	uint8	ICR1;		/* Interrupt Control Register:  Timer 1 */	    
	uint8	ICR2;		/* Interrupt Control Register:  Timer 2 */	    
	uint8	ICR3;		/* Interrupt Control Register:  MBus */	    
	uint8	ICR4;		/* Interrupt Control Register:  UART 1 */	    
	uint8	ICR5;		/* Interrupt Control Register:  UART 2 */	    
	uint8	ICR6;		/* Interrupt Control Register:  DMA 0 */	    
	uint8	ICR7;		/* Interrupt Control Register:  DMA 1 */	    
	uint8	ICR8;		/* Interrupt Control Register:  DMA 2 */	    
	uint8	ICR9;		/* Interrupt Control Register:  DMA 3 */	    
	uint8	ICR10;		/* Interrupt Control Register:  Reserved */    
	uint8	ICR11;		/* Interrupt Control Register:  Reserved */    
} MCF5249_SIM;

#define MCF5249_SIM_RSR_HRST		(0x80)	/* Hard or System Reset */		    
#define MCF5249_SIM_RSR_SWTR		(0x20)	/* Software Watchdog Timer Reset */    

#define MCF5249_SIM_SYPCR_SWE		(0x80)	/* Software Watchdog Enable */	    
#define MCF5249_SIM_SYPCR_SWRI		(0x40)	/* SW Reset/Interrupt Select */	    
#define MCF5249_SIM_SYPCR_SWT_2_9	(0x00)	/* SW Timeout: 2^9  / Sys Freq */	    
#define MCF5249_SIM_SYPCR_SWT_2_11	(0x08)	/* SW Timeout: 2^11 / Sys Freq */	    
#define MCF5249_SIM_SYPCR_SWT_2_13	(0x10)	/* SW Timeout: 2^13 / Sys Freq */	    
#define MCF5249_SIM_SYPCR_SWT_2_15	(0x18)	/* SW Timeout: 2^15 / Sys Freq */	    
#define MCF5249_SIM_SYPCR_SWT_2_18	(0x20)	/* SW Timeout: 2^18 / Sys Freq */	    
#define MCF5249_SIM_SYPCR_SWT_2_20	(0x28)	/* SW Timeout: 2^20 / Sys Freq */	    
#define MCF5249_SIM_SYPCR_SWT_2_22	(0x30)	/* SW Timeout: 2^22 / Sys Freq */	    
#define MCF5249_SIM_SYPCR_SWT_2_24	(0x38)	/* SW Timeout: 2^24 / Sys Freq */	    
#define MCF5249_SIM_SYPCR_SWTA		(0x04)	/* SW Transfer Acknowledge Enable */   
#define MCF5249_SIM_SYPCR_SWTAVAL	(0x02)	/* SW Transfer Acknowledge Valid */    

#define MCF5249_SIM_SWSR_55			(0x55)		/* Write $55 to SWSR */	    
#define MCF5249_SIM_SWSR_AA			(0xaa)		/* Write $AA to SWSR */	    
	
#define MCF5249_SIM_PAR_ADDR31		(0x8000)	/* Assign Pin as ADDR31 */	    
#define MCF5249_SIM_PAR_ADDR30		(0x4000)	/* Assign Pin as ADDR30 */	    
#define MCF5249_SIM_PAR_ADDR29		(0x2000)	/* Assign Pin as ADDR29 */	    
#define MCF5249_SIM_PAR_ADDR28		(0x1000)	/* Assign Pin as ADDR28 */	    
#define MCF5249_SIM_PAR_ADDR27		(0x0800)	/* Assign Pin as ADDR27 */	    
#define MCF5249_SIM_PAR_ADDR26		(0x0400)	/* Assign Pin as ADDR26 */	    
#define MCF5249_SIM_PAR_ADDR25		(0x0200)	/* Assign Pin as ADDR25 */	    
#define MCF5249_SIM_PAR_ADDR24		(0x0100)	/* Assign Pin as ADDR24 */	    
#define MCF5249_SIM_PAR_XTIP		(0x0080)	/* Assign Pin as XTIP */	    
#define MCF5249_SIM_PAR_DREQ0		(0x0040)	/* Assign Pin as DREQ0 */	    
#define MCF5249_SIM_PAR_DREQ1		(0x0020)	/* Assign Pin as DREQ1 */	    
#define MCF5249_SIM_PAR_TM2			(0x0010)	/* Assign Pin as TM2 */	    
#define MCF5249_SIM_PAR_TM1			(0x0008)	/* Assign Pin as TM1 */	    
#define MCF5249_SIM_PAR_TM0			(0x0004)	/* Assign Pin as TM0 */	    
#define MCF5249_SIM_PAR_TT1			(0x0002)	/* Assign Pin as TT1 */	    
#define MCF5249_SIM_PAR_TT0			(0x0001)	/* Assign Pin as TT0 */	    
	
#define MCF5249_SIM_IRQPAR_2		(0x80)		/* IRQ[5] pin to Int IL 4, not 5 */    
#define MCF5249_SIM_IRQPAR_1		(0x20)		/* IRQ[3] pin to Int IL 6, not 3 */    
#define MCF5249_SIM_IRQPAR_0		(0x10)		/* IRQ[1] pin to Int IL 2, not 1 */    

#define MCF5249_SIM_PLLCR_ENBSTOP	(0x80)			/* Enable CPU STOP Instruction */	    
#define MCF5249_SIM_PLLCR_PLLIPL(a)	(((a)&0x07)<<4)	/* PLL Wake-up IPL */	    

#define MCF5249_SIM_MPARK_PARK(a)	(((a)&0x03)<<6)	/* Default Bus Master */	    
#define MCF5249_SIM_MPARK_E2MCTRL	(0x20)			/* EBus to MBus Arbitration */ 
#define MCF5249_SIM_MPARK_EARBCTRL	(0x10)			/* SBus to EBus Arbitration */ 
#define MCF5249_SIM_MPARK_SHOWDATA	(0x08)			/* Show SBus on EBus */	
#define MCF5249_SIM_MPARK_BCR24BIT	(0x01)			/* BCR is 24 or 16 bit register */    

#define MCF5249_SIM_IPR_DMA3		(0x00020000)	/* Interrupt Pending DMA3 */   
#define MCF5249_SIM_IPR_DMA2		(0x00010000)	/* Interrupt Pending DMA2 */   
#define MCF5249_SIM_IPR_DMA1		(0x00008000)	/* Interrupt Pending DMA1 */  
#define MCF5249_SIM_IPR_DMA0		(0x00004000)	/* Interrupt Pending DMA0 */   
#define MCF5249_SIM_IPR_UART2		(0x00002000)	/* Interrupt Pending UART2 */  
#define MCF5249_SIM_IPR_UART1		(0x00001000)	/* Interrupt Pending UART1 */  
#define MCF5249_SIM_IPR_MBUS		(0x00000800)	/* Interrupt Pending MBUS */   
#define MCF5249_SIM_IPR_TIMER2		(0x00000400)	/* Interrupt Pending TIMER2 */ 
#define MCF5249_SIM_IPR_TIMER1		(0x00000200)	/* Interrupt Pending TIMER1 */ 
#define MCF5249_SIM_IPR_SWT			(0x00000100)	/* Interrupt Pending SWT */    
#define MCF5249_SIM_IPR_EINT7		(0x00000080)	/* Interrupt Pending EINT7 */  
#define MCF5249_SIM_IPR_EINT6		(0x00000040)	/* Interrupt Pending EINT6 */  
#define MCF5249_SIM_IPR_EINT5		(0x00000020)	/* Interrupt Pending EINT5 */  
#define MCF5249_SIM_IPR_EINT4		(0x00000010)	/* Interrupt Pending EINT4 */  
#define MCF5249_SIM_IPR_EINT3		(0x00000008)	/* Interrupt Pending EINT3 */  
#define MCF5249_SIM_IPR_EINT2		(0x00000004)	/* Interrupt Pending EINT2 */ 
#define MCF5249_SIM_IPR_EINT1		(0x00000002)	/* Interrupt Pending EINT1 */ 

#define MCF5249_SIM_IMR_DMA3		(0x00020000)	/* Mask DMA3 */		    
#define MCF5249_SIM_IMR_DMA2		(0x00010000)	/* Mask DMA2 */		    
#define MCF5249_SIM_IMR_DMA1		(0x00008000)	/* Mask DMA1 */		    
#define MCF5249_SIM_IMR_DMA0		(0x00004000)	/* Mask DMA0 */		    
#define MCF5249_SIM_IMR_UART2		(0x00002000)	/* Mask UART2 */		    
#define MCF5249_SIM_IMR_UART1		(0x00001000)	/* Mask UART1 */		    
#define MCF5249_SIM_IMR_MBUS		(0x00000800)	/* Mask MBUS */		    
#define MCF5249_SIM_IMR_TIMER2		(0x00000400)	/* Mask TIMER2 */	    
#define MCF5249_SIM_IMR_TIMER1		(0x00000200)	/* Mask TIMER1 */		    
#define MCF5249_SIM_IMR_SWT			(0x00000100)	/* Mask SWT */		    
#define MCF5249_SIM_IMR_EINT7		(0x00000080)	/* Mask EINT7 */		    
#define MCF5249_SIM_IMR_EINT6		(0x00000040)	/* Mask EINT6 */		    
#define MCF5249_SIM_IMR_EINT5		(0x00000020)	/* Mask EINT5 */		    
#define MCF5249_SIM_IMR_EINT4		(0x00000010)	/* Mask EINT4 */		    
#define MCF5249_SIM_IMR_EINT3		(0x00000008)	/* Mask EINT3 */		    
#define MCF5249_SIM_IMR_EINT2		(0x00000004)	/* Mask EINT2 */		    
#define MCF5249_SIM_IMR_EINT1		(0x00000002)	/* Mask EINT1 */		    

#define MCF5249_SIM_AVCR_AVEC7		(0x80)			/* Auto Vector Ext Interrupt 7 */	    
#define MCF5249_SIM_AVCR_AVEC6		(0x40)			/* Auto Vector Ext Interrupt 6 */	    
#define MCF5249_SIM_AVCR_AVEC5		(0x20)			/* Auto Vector Ext Interrupt 5 */	    
#define MCF5249_SIM_AVCR_AVEC4		(0x10)			/* Auto Vector Ext Interrupt 4 */	    
#define MCF5249_SIM_AVCR_AVEC3		(0x08)			/* Auto Vector Ext Interrupt 3 */	    
#define MCF5249_SIM_AVCR_AVEC2		(0x04)			/* Auto Vector Ext Interrupt 2 */	    
#define MCF5249_SIM_AVCR_AVEC1		(0x02)			/* Auto Vector Ext Interrupt 1 */