compactpci_system_16000x23335_2x135_2x132_114pin_6u.prjpcb

cpci PCB模板

[Design]
Version=1.0
HierarchyMode=0
ChannelRoomNamingStyle=0
OutputPath=
LogFolderPath=
ReleasesFolder=
ReleaseVaultGUID=9F0439D8-5E13-4286-B92A-0416224E50A9
ReleaseVaultName=Altium Shanghai
ChannelDesignatorFormatString=$Component_$RoomName
ChannelRoomLevelSeperator=_
OpenOutputs=1
ArchiveProject=0
TimestampOutput=0
SeparateFolders=0
TemplateLocationPath=
PinSwapBy_Netlabel=1
PinSwapBy_Pin=1
AllowPortNetNames=0
AllowSheetEntryNetNames=1
AppendSheetNumberToLocalNets=0
NetlistSinglePinNets=0
DefaultConfiguration=
UserID=0xFFFFFFFF
DefaultPcbProtel=1
DefaultPcbPcad=0
ReorderDocumentsOnCompile=1
NameNetsHierarchically=0
PowerPortNamesTakePriority=0
PushECOToAnnotationFile=1
DItemRevisionGUID=

[Document1]
DocumentPath=CompactPCI_System_16000X23335_2X135_2X132_114PIN_6U.PcbDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0

[Document2]
DocumentPath=CompactPCI_System_16000X23335_2X135_2X132_114PIN_6U.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=0
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0

[Document3]
DocumentPath=CompactPCI_System_16000X23335_2X135_2X132_114PIN_6U.Harness
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0

[Parameter1]
Name=Template Source URL2
Value=

[Parameter2]
Name=Template Source URL
Value=www.picmg.org

[Parameter3]
Name=Template Source Revision Date
Value=R3.0, Oct-1999

[Parameter4]
Name=Template Source Organization
Value=PICMG 2.0

[Parameter5]
Name=Template Source Name
Value=CompactPCI Specification

[Parameter6]
Name=Template Source Document
Value=Compact PCI PICMG 2.0 R3.0.pdf

[Parameter7]
Name=Template Revision Date
Value=Jun-2011

[Parameter8]
Name=Template Notes
Value=- Nominal values used, all dimensions are mm.  - Generic footprints used.  - Pins marked as BRSVPxxx and RSV are reserved for future definition, see Compact PCI PICMG 2.0 R3.0.pdf, page 60.  - Top Layer component height rule derived from Cross Section, see Compact PCI PICMG 2.0 R3.0.pdf, Page 47.  - Bottom Layer component height assumes no solder side cover and complies with section 4.1.8, see Compact PCI PICMG 2.0 R3.0.pdf, Page 39, 47.  - Boards with bottom layer components or through-hole pins have additional requirements, see Compact PCI PICMG 2.0 R3.0.pdf, Page 39.  - Stackup is not specified in Compact PCI PICMG 2.0 R3.0.pdf, nor implemented in this template.

[Parameter9]
Name=Template Family
Value=CompactPCI

[Parameter10]
Name=ProjectTitle
Value=CompactPCI System 6U

[Parameter11]
Name=ProjectOrganization
Value=Altium

[Parameter12]
Name=ProjectAddress4
Value=Shanghai 200335, China

[Parameter13]
Name=ProjectAddress3
Value=No.168 Linhong Road

[Parameter14]
Name=ProjectAddress2
Value=Level 3 - Building 3

[Parameter15]
Name=ProjectAddress1
Value=IBP Shanghai

[PCBConfiguration1]
ReleaseItemId=1413F625-0B64-4763-A9D9-086A6F8866FF
CurrentRevision=0C62BBF5-107A-46AA-B079-F4FBC31EA70B
Name=Default Configuration
Variant=[No Variations]
GenerateBOM=1

[OutputGroup1]
Name=Netlist Outputs
Description=
TargetPrinter=HP LaserJet P2015 PCL6
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=EDIF
OutputName1=EDIF for PCB
OutputDocumentPath1=
OutputVariantName1=
OutputDefault1=0
OutputType2=MultiWire
OutputName2=MultiWire
OutputDocumentPath2=
OutputVariantName2=
OutputDefault2=0
OutputType3=ProtelNetlist
OutputName3=Protel
OutputDocumentPath3=
OutputVariantName3=
OutputDefault3=0
OutputType4=VHDL
OutputName4=VHDL File
OutputDocumentPath4=
OutputVariantName4=
OutputDefault4=0
OutputType5=XSpiceNetlist
OutputName5=XSpice Netlist
OutputDocumentPath5=
OutputVariantName5=
OutputDefault5=0
OutputType6=Protel2Netlist
OutputName6=Protel2 Netlist
OutputDocumentPath6=
OutputVariantName6=
OutputDefault6=0
OutputType7=CadnetixNetlist
OutputName7=Cadnetix Netlist
OutputDocumentPath7=
OutputVariantName7=
OutputDefault7=0
OutputType8=CalayNetlist
OutputName8=Calay Netlist
OutputDocumentPath8=
OutputVariantName8=
OutputDefault8=0
OutputType9=EESofNetlist
OutputName9=EESof Netlist
OutputDocumentPath9=
OutputVariantName9=
OutputDefault9=0
OutputType10=IntergraphNetlist
OutputName10=Intergraph Netlist
OutputDocumentPath10=
OutputVariantName10=
OutputDefault10=0
OutputType11=MentorBoardStationNetlist
OutputName11=Mentor BoardStation Netlist
OutputDocumentPath11=
OutputVariantName11=
OutputDefault11=0
OutputType12=OrCadPCB2Netlist
OutputName12=Orcad/PCB2 Netlist
OutputDocumentPath12=
OutputVariantName12=
OutputDefault12=0
OutputType13=PADSNetlist
OutputName13=PADS ASCII Netlist
OutputDocumentPath13=
OutputVariantName13=
OutputDefault13=0
OutputType14=Pcad
OutputName14=Pcad for PCB
OutputDocumentPath14=
OutputVariantName14=
OutputDefault14=0
OutputType15=PCADNetlist
OutputName15=PCAD Netlist
OutputDocumentPath15=
OutputVariantName15=
OutputDefault15=0
OutputType16=PCADnltNetlist
OutputName16=PCADnlt Netlist
OutputDocumentPath16=
OutputVariantName16=
OutputDefault16=0
OutputType17=RacalNetlist
OutputName17=Racal Netlist
OutputDocumentPath17=
OutputVariantName17=
OutputDefault17=0
OutputType18=RINFNetlist
OutputName18=RINF Netlist
OutputDocumentPath18=
OutputVariantName18=
OutputDefault18=0
OutputType19=SciCardsNetlist
OutputName19=SciCards Netlist
OutputDocumentPath19=
OutputVariantName19=
OutputDefault19=0
OutputType20=SIMetrixNetlist
OutputName20=SIMetrix
OutputDocumentPath20=
OutputVariantName20=
OutputDefault20=0
OutputType21=SIMPLISNetlist
OutputName21=SIMPLIS
OutputDocumentPath21=
OutputVariantName21=
OutputDefault21=0
OutputType22=TangoNetlist
OutputName22=Tango Netlist
OutputDocumentPath22=
OutputVariantName22=
OutputDefault22=0
OutputType23=TelesisNetlist
OutputName23=Telesis Netlist
OutputDocumentPath23=
OutputVariantName23=
OutputDefault23=0
OutputType24=Verilog
OutputName24=Verilog File
OutputDocumentPath24=
OutputVariantName24=
OutputDefault24=0
OutputType25=WireListNetlist
OutputName25=WireList Netlist
OutputDocumentPath25=
OutputVariantName25=
OutputDefault25=0

[OutputGroup2]
Name=Simulator Outputs
Description=
TargetPrinter=HP LaserJet P2015 PCL6
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=AdvSimNetlist
OutputName1=Mixed Sim
OutputDocumentPath1=
OutputVariantName1=
OutputDefault1=0
OutputType2=SIMetrix_Sim
OutputName2=SIMetrix
OutputDocumentPath2=
OutputVariantName2=
OutputDefault2=0
OutputType3=SIMPLIS_Sim
OutputName3=SIMPLIS
OutputDocumentPath3=
OutputVariantName3=
OutputDefault3=0

[OutputGroup3]
Name=Documentation Outputs
Description=
TargetPrinter=HP LaserJet P2015 PCL6
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=Composite
OutputName1=Composite Drawing
OutputDocumentPath1=
OutputVariantName1=
OutputDefault1=0
PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
OutputType2=PCB Print
OutputName2=PCB Prints
OutputDocumentPath2=
OutputVariantName2=
OutputDefault2=0
PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
OutputType3=Schematic Print
OutputName3=Schematic Prints
OutputDocumentPath3=
OutputVariantName3=
OutputDefault3=0
PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
OutputType4=Assembler Source Print
OutputName4=Assembler Source Prints
OutputDocumentPath4=
OutputVariantName4=
OutputDefault4=0
PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
OutputType5=C Source Print
OutputName5=C Source Prints
OutputDocumentPath5=
OutputVariantName5=
OutputDefault5=0
PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
OutputType6=C/C++ Header Print
OutputName6=C/C++ Header Prints
OutputDocumentPath6=
OutputVariantName6=
OutputDefault6=0
PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
OutputType7=C++ Source Print
OutputName7=C++ Source Prints
OutputDocumentPath7=
OutputVariantName7=
OutputDefault7=0
PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
OutputType8=Logic Analyser Print
OutputName8=Logic Analyser Prints
OutputDocumentPath8=